ST ST10F276E - Protected Bits; Table 1. Protected Bit

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UM0404 Architectural overview
1.6 Protected bits
The ST10F276x MCU provides up to 106 protected bits. These bits are modified by the on-
chip hardware during special events such as Power-On reset, power failure, or application
hardware. These bits cannot be modified by some wrong software accesses.
Note: Σ = 106 protected bit.
Table 1. Protected bit
Register Bit name Notes
T2IC, T3IC, T4IC T2IR, T3IR, T4IR GPT1 timer interrupt request flags
T5IC, T6IC T5IR, T6IR GPT2 timer interrupt request flags
CRIC CRIR GPT2 CAPREL interrupt request flag
T3CON, T6CON T3OTL, T6OTL GPTx timer output toggle latches
T0IC, T1IC T0IR, T1IR CAPCOM1 timer interrupt request flags
T7IC, T8IC T7IR, T8IR CAPCOM2 timer interrupt request flags
S0TIC, S0TBIC S0TIR, S0TBIR ASC0 transmit (buffer) interrupt request flags
S0RIC, S0EIC S0RIR, S0EIR ASC0 receive/error interrupt request flags
S0CON S0REN ASC0 receiver enable flag
SSCTIC, SSCRIC SSCTIR, SSCRIR SSC transmit/receive interrupt request flags
SSCEIC SSCEIR SSC error interrupt request flag
SSCCON SSCBSY SSC busy flag
SSCCON SSCBE, SSCPE SSC error flags
SSCCON SSCRE, SSCTE SSC error flags
ADCIC, ADEIC ADCIR, ADEIR ADC end-of-conversion/overrun interrupt request flags
ADCON ADST, ADCRQ ADC start flag / injection request flag
CC31IC...CC16IC CC31IR...CC16IR CAPCOM2 interrupt request flags
CC15IC...CC0IC CC15IR...CC0IR CAPCOM1 interrupt request flags
PWMIC PWMIR PWM module interrupt request flag
TFR TFR.15,14,13 Class A trap flags
TFR TFR.7,3,2,1,0 Class B trap flags
P2 P2.15...P2.0 All bits of Port2
P7 P7.7...P7.0 All bits of Port7
P8 P8.7...P8.0 All bits of Port8
XPyIC (y=3...0) XPyIR (y=3...0) X-Peripheral y interrupt request flag