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UM0404 Memory organization
Context Pointer register (CP) is active at a given time. Selecting a new active register bank
is simply done by updating the CP register.
A particular Switch Context (SCXT) instruction performs register bank switching and an
automatic saving of the previous context. The number of implemented register banks
(arbitrary sizes) is only limited by the size of the available IRAM.
Details on using, switching and overlapping register banks are described in Register
Banking Section 27.2: Register banking on page 551.
2.3.3 PEC source and destination pointers
The 16 word locations in the IRAM from 00’FCE0h to 00’FCFEh are provided as source and
destination address pointers for data transfers on the eight PEC channels. Each channel
uses a pair of pointers stored in two subsequent word locations with the source pointer
(SRCPx) on the lower and the destination pointer (DSTPx) on the higher word address (x =
7...0) (see Figure 7 on page 48).
Whenever a PEC data transfer is performed, the pair of source and destination pointers
selected by the specified PEC channel number is accessed independently of the current
DPP register contents. The locations referred to by these pointers are accessed
independently of the current DPP register contents. If a PEC channel is not used, the
corresponding pointer locates the area available and can be used for word or byte data
storage.
For more details about the use of the source and destination pointers for PEC data
transfers, see Section 27: System programming on page 545.
Table 6. Mapping of general purpose registers to RAM addresses
IRAM address Byte registers Word register
(CP) + 1Eh --- R15
(CP) + 1Ch --- R14
(CP) + 1Ah --- R13
(CP) + 18h --- R12
(CP) + 16h --- R11
(CP) + 14h --- R10
(CP) + 12h --- R9
(CP) + 10h --- R8
(CP) + 0Eh RH7, RL7 R7
(CP) + 0Ch RH6, RL6 R6
(CP) + 0Ah RH5, RL5 R5
(CP) + 08h RH4, RL4 R4
(CP) + 06h RH3, RL3 R3
(CP) + 04h RH2, RL2 R2
(CP) + 02h RH1, RL1 R1
(CP) + 00h RH0, RL0 R0
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