ST ST10F276E - Exiting the Hold State; Figure 70. External Bus Arbitration, Releasing the Bus

The external bus interface UM0404
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Figure 70. External bus arbitration, releasing the bus
Note: The ST10F276 will complete the currently running bus cycle before granting bus access as
indicated by the broken lines. This may delay hold acknowledge compared to this figure.
The figure above shows the first possibility for BREQ
to get active. During bus hold pin
P3.12 is switched back to its standard function and is then controlled by DP3.12 and P3.12.
Keep DP3.12 = ‘0’ in this case to ensure floating in hold mode.
8.6.3 Exiting the hold state
The external bus master returns the access rights to the ST10F276 by driving the HOLD
input high. After synchronizing this signal the ST10F276 will drive the HLDA
output high,
actively drive the control signals and resume executing external bus cycles if required.
Depending on the arbitration logic, the external bus can be returned to the ST10F276 under
two circumstances:
• The external master does no more require access to the shared resources and gives
up its own access rights.
• The ST10F276 needs access to the shared resources and demands this by activating
its BREQ
output.
The arbitration logic may then deactivate the other master’s HLDA
and so free the external
bus for the ST10F276, depending on the priority of the different masters.
Note: The Hold State is not terminated by clearing bit HLDEN.
HOLD
HLDA
BREQ
CSx
Other
Signals