ST ST10F276E - Table 53. PWM Module Channel Specific Register Addresses

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UM0404 Pulse width modulation module
This type of comparison allows a flexible control of the PWM signal. For the register
locations refer to the Table 53.
PWM control register PWMCON0
Register PWMCON0 controls the function of the timers of the four PWM channels and the
channel specific interrupts. Having the control bit organized in functional groups allows to
start or to stop all the four PWM timers simultaneously with one bit-field instruction.
PWMCON0 (FF30h / 98h) SFR Reset Value: 0000h
PWM control register PWMCON1
Register PWMCON1 controls the operating modes and the outputs of the four PWM
channels. The basic operating mode for each channel (standard = edge aligned, or
symmetrical = center aligned PWM mode) is selected by the mode bit PMx. Burst mode
(channels 0 and 1) and single shot mode (channel 2 or 3) are selected by separate control
Table 53. PWM module channel specific register addresses
Register Address Reg. space Register Address Reg. space
PW0 FE30h / 18h SFR PT0 F030h / 18h ESFR
PW1 FE32h / 19h SFR PT1 F032h / 19h ESFR
PW2 FE34h / 1Ah SFR PT2 F034h / 1Ah ESFR
PW3 FE36h / 1Bh SFR PT3 F036h / 1Bh ESFR
These registers are not bit-addressable.
PP0 F038h / 1Ch ESFR
PP1 F03Ah / 1Dh ESFR
PP2 F03Ch / 1Eh ESFR
PP3 F03Eh / 1Fh ESFR
1514131211109876543210
PIR3 PIR2 PIR1 PIR0 PIE3 PIE2 PIE1 PIE0 PTI3 PTI2 PTI1 PTI0 PTR3 PTR2 PTR1 PTR0
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
Bit Function
PTRx
PWM Timer x Run Control bit
‘0’: Timer PTx is disconnected from its input clock
‘1’: Timer PTx is running
PTIx
PWM Timer x Input Clock Selection
‘0’: Timer PTx clocked with CLK
CPU
‘1’: Timer PTx clocked with CLK
CPU
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PIEx
PWM Channel x Interrupt Enable Flag
‘0’: Interrupt from channel x disabled
‘1’: Interrupt from channel x enabled
PIRx
PWM Channel x Interrupt Request Flag
‘0’: No interrupt request from channel x
‘1’: Channel x interrupt pending (must be reset via software)