High-speed synchronous serial interface UM0404
278/564 DocID13284 Rev 2
(SSCPO = ‘0’) will drive the alternate data output and (via the AND) the port pin SCLK
immediately low. To avoid this, use the following sequence:
• Select the clock idle level (SSCPO = ‘x’)
• Load the port output latch with the desired clock idle level (P3.13 = ‘x’)
• Switch the pin to output (DP3.13 = ‘1’)
• Enable the SSC (SSCEN = ‘1’)
• If SSCPO = ‘0’: enable alternate data output (P3.13 = ‘1’)
The same mechanism as for selecting a slave for transmission (separate select lines or
special commands) may also be used to move the role of the master to another device in
the network. In this case the previous master and the future master (previous slave) will
have to toggle their operating mode (SSCMS) and the direction of their port pins (see
description above).
12.2 Half duplex operation
In a half duplex configuration only one data line is necessary for both receiving and
transmitting of data. The data exchange line is connected to both pins MTSR and MRST of
each device, the clock line is connected to the SCLK pin.
The master device controls the data transfer by generating the shift clock, while the slave
devices receive it. Due to the fact that all transmit and receive pins are connected to the one
data exchange line, serial data may be moved between arbitrary stations.
Similar to full duplex mode there are two ways to avoid collisions on the data exchange line:
• Only the transmitting device may enable its transmit pin driver
• The non-transmitting devices use open drain output and only send ones.
Since the data inputs and outputs are connected together, a transmitting device will clock in
its own data at the input pin (MRST for a master device, MTSR for a slave). By these means
any corruptions on the common data exchange line are detected, where the received data is
not equal to the transmitted data.
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