Memory organization UM0404
44/564 DocID13284 Rev 2
Code fetches are always made on even byte addresses. The last valid code location must
contain a branch instruction (unconditional), because sequential boundary crossing from
internal Flash to external memory is not supported and causes erroneous results.
Any word and byte data read accesses may use the indirect or long 16-bit addressing
modes. There is no short addressing mode for internal Flash operands. Any word data
access is made to an even byte address.
For PEC data transfers the internal Flash can be accessed independently of the contents of
the DPP registers via the PEC source and destination pointers.
The internal Flash is not provided for single bit storage, and therefore it is not bit
addressable.
The first 32 Kbytes of the internal Flash may be mapped into segment 0 or segment 1 under
software control. Section 27.10: Handling the internal Flash on page 556 describes the
mapping procedures and precautions.
2.3 IRAM and SFR area
The IRAM/SFR area is located within data page 3 and provides access to the 2 Kbyte IRAM
(organized as 1K x 16) and to two 512 byte blocks of Special Function Registers (SFRs).
The IRAM is used as:
• System stack (programmable size),
• General purpose register banks (GPRs),
• Source and destination pointers for the peripheral event controller (PEC),
• Variable and other data storage, or Code storage.
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