ST ST10F276E - Trap Functions; Table 21. Trap Priorities

Interrupt and trap functions UM0404
128/564 DocID13284 Rev 2
To enable the interrupt in the interrupt controller, the Interrupt Control Register XP3IC has to
be initialized. The associated interrupt vector is called XP3INT located at address 10Ch
(trap number 43h).
XP3IC (F19Eh / CFh) ESFR Reset Value: - - 00h
Note: Refer to Section 5.1.3: Interrupt control registers on page 100 for an explanation of the
control fields.
5.8 Trap functions
Traps interrupt the current execution like standard interrupts do. However, trap functions
offer the possibility to bypass the interrupt system prioritization process in cases where
immediate system reaction is required. Trap functions are not maskable and always have
priority over interrupt requests on any priority level.
The ST10F276 provides two different kinds of trap mechanisms:
• Hardware traps are triggered by events that occur during program execution (like
illegal access or undefined opcode);
• Software traps are initiated via an instruction within the current execution flow.
The trap priorities are summarized in Table 21.
Bit Function
FLCLR.x
Interrupt Flag x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR3SEL register.
Writing a ‘0’ has no effect.
IECLR.x
Interrupt Enable x CLEAR (x=7...0)
Writing a ‘1’ will clear the corresponding bit x in XIR3SEL register.
Writing a ‘0’ has no effect.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
--------XP3IRXP3IE ILVL GLVL
RW RW RW RW
Table 21. Trap priorities
Exception condition Trap flag
Trap
vector
Vector
location
Trap
number
Trap
priority
RESET Functions:
Hardware RESET
Software RESET
Watchdog Timer Overflow
RESET
RESET
RESET
00’0000h
00’0000h
00’0000h
00h
00h
00h
MAXIMAL
III
III
III
Class A Hardware Traps:
Non-Maskable Interrupt
Stack Overflow
Stack Underflow
NMI
STKOF
STKUF
NMITRAP
STOTRAP
STUTRAP
00’0008h
00’0010h
00’0018h
02h
04h
06h
II
II
II