The general purpose timer units UM0404
238/564 DocID13284 Rev 2
Figure 93. Block diagram of core timer T6 in counter mode
The maximum input frequency which is allowed in counter mode is f
CPU
/ 8. To ensure that a
transition of the count input signal which is applied to T6IN is correctly recognized, its level
should be held high or low for at least four CPU clock cycles before it changes.
GPT2 auxiliary timer T5
The auxiliary timer T5 can be configured for timer, gated timer, or counter mode with the
same options for the timer frequencies and the count signal as the core timer T6. In addition
to these three counting modes, the auxiliary timer can be concatenated with the core timer.
The auxiliary timer has no output toggle latch and no alternate output function. The
individual configuration for timer T5 is determined by its bit-addressable control register
T5CON. Note that functions which are present in both timers of block GPT2 are controlled in
the same bit positions and in the same manner in each of the specific control registers.
T5CON (FF46h / A3h) SFR Reset Value: 0000h
Edge
Select
T6R
MUX
T6UDE
Core Timer T6
T6IR
Interrupt
Request
T6OTL
T6OE
T6OUT
Up/Down
XOR
1
0
T6UD
T6EUD
T6M
T6IN
P5.12
P5.10
P3.1
Table 40. GPT2 core timer T6 (counter mode) input edge selection
T6I Triggering edge for counter increment / decrement
0 0 0 None. Counter T6 is disabled
0 0 1 Positive transition (rising edge) on T6IN
0 1 0 Negative transition (falling edge) on T6IN
0 1 1 Any transition (rising or falling edge) on T6IN
1 X X Reserved. Do not use this combination
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
T5SC T5CLR CI - - CT3 T5UDE T5UD T5R - T5M T5I
RW RW RW RW RW RW RW RW RW
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