Memory organization UM0404
50/564 DocID13284 Rev 2
Any word and byte data read accesses may use the indirect or long 16-bit addressing
modes. There is no short addressing mode for XRAM operands. Any word data access is
made to an even byte address. For PEC data transfers XRAM1 can be accessed
independently of the contents of the DPP registers, via the PEC source and destination
pointers. XRAM2 is not PEC addressable, since not mapped in code segment 0.
The on-chip XRAM is accessed without any wait-states, using 16-bit de-multiplexed bus
cycles which takes one instruction cycle. Even if the XRAM is used as external memory, it
does not occupy BUSCONx / ADDRSELx registers, but it is selected via additional
dedicated XBCON / XADRS registers. In general, these registers are mask-programmed
and are not user accessible. The address area of 00’E000h to 00’E7FFh is reserved for
XRAM1 accesses, and the address area of 0F’0000h - 0F’FFFFh is reserved for XRAM2
accesses. In ST10F276 the register XADRS3 used for XRAM2 and XFLASH memory range
is user programmable: this allows to redefine the size and starting address of the memory
window, making possible to play with on-chip and external memory resources (refer to
Section 8.7: The XBUS interface on page 207 for details).
2.4.1 XRAM access via external masters
When bit XPER-SHARE in register SYSCON is set the on-chip XRAM of the ST10F276 can
be accessed by an external master during hold mode, via the ST10F276’s bus interface.
These external accesses must use the same configuration as the internally programmed.
No wait-states are required.
The configuration in register SYSCON cannot be changed after the execution of the EINIT
instruction.
External accesses to the other XBUS peripherals are not guaranteed in terms of AC
Timings. Note that setting XPER-SHARE Mode affects the system configuration: since the
bus control functions BREQ, HLDA and HOLD are mapped as alternate functions of
P6(7:5), the XSSC module is not accessible when arbitration is in use. For similar reasons,
in case segment lines A(23:20) on Port4 have to be used (SALSEL = 10), the CAN1, CAN2
and I
2
C modules might not be accessible.
2.5 External memory space
The ST10F276 is capable of using an address space of up to 16 Mbytes. Only parts of this
address space are occupied by internal memory areas. All addresses which are not used for
on-chip memory (Flash) or for registers, may refer to external memory locations. This
external memory is accessed via the ST10F276’s external bus interface.
Four memory bank sizes are supported:
• Non-segmented mode: 64 Kbytes with A15...A0 on PORT0 or PORT1
• 2-bit segmented mode: 256 Kbytes with A17...A16 on Port4 and A15...A0 on PORT0 or
PORT1
• 4-bit segmented mode: 1 Mbyte with A19...A16 on Port4 and A15...A0 on PORT0 or
PORT1
• 8-bit segmented mode: 16 Mbytes with A23...A16 on Port4 and A15...A0 on PORT0 or
PORT1
Each bank can be directly addressed via the address bus while the programmable chip
select signals that can be used to select various memory banks.
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