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UM0404 Multiply-accumulate unit (MAC)
4.2.9 The accumulator shifter
The accumulator shifter is a parallel shifter with a 40-bit input and a 40-bit output. The
source accumulator shifting operations are:
• No shift (Unmodified)
• Up to 8-bit Arithmetic Left Shift
• Up to 8-bit Arithmetic Right Shift
Notice that MSW.ME, MSW.MSV and MSW.MSL bits (see MSW register description) are
affected by left shifts, therefore, if the saturation detection is enabled (MCW.MS bit is set),
the behavior is similar to the one of the Adder/Subtracter.
Some precautions are required in case of left shift with enabled saturation. If
MSW.MAE bit-field (most significant byte of the 40-bit Signed Accumulator) contains
significant bits, then the 32-bit value in the accumulator is generally saturated. However, it is
possible that a left shift may move out of the Accumulator some significant bits. The 40-bit
result will be misinterpreted and will be either not saturated or saturated wrong. There is a
chance that the result of a left shift may produce a result which can saturate an original
positive number to the minimum negative value, or vice versa.
4.2.10 Repeat unit
The MAC includes a repeat unit allowing the repetition of some co-processor instructions up
to 2
13
(8192) times. The repeat count may be specified either by an immediate value (up to
31 times) or by the content of the Repeat Count (bits 12 to 0) in the MAC Repeat Word
(MRW). If the Repeat Count equals “N” the instruction will be executed “N+1” times. At each
iteration of a cumulative instruction the Repeat Count is tested for zero. If it is zero the
instruction is terminated else the Repeat Count is decremented and the instruction is
repeated. During such a repeat sequence, the Repeat Flag in MRW is set until the last
execution of the repeated instruction.
The syntax of repeated instructions is shown in the following examples:
In example 1, the instruction is repeated according to a 5-bit immediate value. The Repeat
Count in MRW is automatically loaded with this value minus one (MRW=23).
In this second example, the instruction is repeated according to the Repeat Count in MRW.
Notice that due to the pipeline processing at least one instruction should be inserted
between the write of MRW and the next repeated instruction.
Repeat sequences may be interrupted. When an interrupt occurs during a repeat sequence,
the sequence is stopped and the interrupt routine is executed. The repeat sequence
resumes at the end of the interrupt routine. During the interrupt, MR remains set, indicating
that a repeated instruction has been interrupted and the Repeat Count holds the number
(minus 1) of repetition that remains to complete the sequence. If the Repeat Unit is used in
1 Repeat #24 times
CoMAC[IDX0+],[R0+] ; repeated 24 times
2 MOV MRW, #00FFh ; load MRW with 255
NOP ; instruction latency
Repeat MRW times
CoMACM [IDX1-],[R2+] ; repeated 256 times
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