ST ST10F276E - Figure 66. READY;READY Controlled Bus Cycles

DocID13284 Rev 2 195/564
UM0404 The external bus interface
The synchronous READY/READY (SREADY / SREADY) provides the fastest bus cycles,
but requires setup and hold times to be met. The CLKOUT signal should be enabled and
may be used by the peripheral logic to control the READY/READY
timing in this case.
The asynchronous READY/READY
(AREADY / AREADY) is less restrictive, but requires
additional wait-states caused by the internal synchronization. As the asynchronous
READY/READY
is sampled earlier (see Figure 66) programmed wait-states may be
necessary to provide proper bus cycles (see also notes on “normally-ready” peripherals
below).
Figure 66. READY/READY
controlled bus cycles
A READY/READY
signal (especially asynchronous READY/READY) that has been
activated by an external device may be deactivated in response to the trailing (rising) edge
of the respective command (RD
or WR).
Note: When the READY/READY
function is enabled for a specific address window, each bus
cycle within this window must be terminated with an active READY/READY
signal.
Otherwise the controller hangs until the next reset. A time-out function is only provided by
the watchdog timer.
Combining the READY function with predefined wait-states is advantageous in two
cases:
• Memory components with a fixed access time and peripherals operating with
READY/READY
may be grouped into the same address window. The (external) wait-
state control logic in this case would activate READY/READY
either upon the
memory’s chip select or with the peripheral’s READY/READY
output. After the
predefined number of wait-states the ST10F276 will check its READY/READY
line to
determine the end of the bus cycle. For a memory access it will be low already (see
Figure 66), for a peripheral access it may be delayed. As memories tend to be faster
than peripherals, there should be no impact on system performance.
• When using the READY/READY
function with so-called “normally-ready” peripherals, it
may lead to erroneous bus cycles, if the READY/READY
line is sampled too early.
These peripherals pull their READY/READY
output low, while they are idle. When they
are accessed, they deactivate READY/READY
until the bus cycle is complete, then
ALE
RD
/WR
SREADY
AREADY
SREADY
AREADY
Bus Cycle with active READY or READY
Bus Cycle Extended via READY or READY
1.WS 2.WS
1.WS 2.WS
Evaluation (sampling) of the READY/READY input