ST ST10F276E - SDA;SCL Line Control

I
2
C interface UM0404
394/564 DocID13284 Rev 2
The speed of the I
2
C interface may be selected between Standard (0-100kHz) and Fast I
2
C
(100-400kHz).
20.2.3 SDA/SCL line control
Transmitter mode: the interface holds the clock line low before transmission to wait for the
microcontroller to write the byte in the Data Register.
Receiver mode: the interface holds the clock line low after reception to wait for the
microcontroller to read the byte in the Data Register.
The SCL frequency (F
SCL
) is controlled by a programmable clock divider which depends on
the I
2
C bus mode.
When the I
2
C cell is enabled by setting bit XI2CEN in XPERCON register, pins P4.4 and
P4.7 (where SCL and SDA are respectively mapped as alternate functions) are
automatically configured as bidirectional open-drain: the value of the external pull-up
resistor depends on the application. P4, DP4 and ODP4 cannot influence the pin
configuration.
When the I
2
C cell is disabled (clearing bit XI2CEN), P4.4 and P4.7 pins are standard I/O
controlled by P4, DP4 and ODP4.