ST ST10F276E - Figure 209. PORT0 Bits Latched into the Different Registers after Reset; Table 65. PORT0 Latched Configuration for the Different Reset Events

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DocID13284 Rev 2 497/564

UM0404 System reset

Figure 209. PORT0 bits latched into the different registers after reset

Table 65. PORT0 latched configuration for the different reset events

X : Pin is sampled

- : Pin is not sampled

PORT0

Clock Options

Segm. Addr. Lines

Chip Selects

WR config.

Bus Type

Reserved

BSL

Reserved

Adapt Mode

Emu Mode

Sample event

P0H.7

P0H.6

P0H.5

P0H.4

P0H.3

P0H.2

P0H.1

P0H.0

P0L.7

P0L.6

P0L.5

P0L.4

P0L.3

P0L.2

P0L.1

P0L.0

Software Reset - - - XXXXXXX - - ----

Watchdog Reset - - - XXXXXXX - - ----

Synchronous Short Hardware Reset - - - XXXXXXXXXXXXX

Synchronous Long Hardware Reset XXXXXXXXXXXXXXXX

Asynchronous Hardware Reset XXXXXXXXXXXXXXXX

Asynchronous Power-On Reset XXXXXXXXXXXXXXXX

L.5 L.4 L.3 L.2 L.1 L.0H. H. H. H. L.7 L.6H. H. H. H.

RP0H

Clock Port4

Logic

Port6

Logic

SYSCON BUSCON0

Internal Control Logic

P0L.7

BYTDIS

WRCFG

PORT0

Bootstrap Loader

Generator

EA / VSTBY

ROMEN

Main Page

Default Chapter2
- Table of Contents2
Architectural Overview22
- Basic CPU Concepts and Optimization22
- On-Chip System Resources27
- Clock Generator30
- On-Chip Peripheral Blocks32
- Real Time Clock38
- Protected Bits39
- Table 1. Protected Bit39
Memory Organization40
- Word, Byte and Bit Storage41
- Figure 4. ST10F276 Memory Mapping (User Mode: Flash Read Operation)41
- On-Chip Flash42
- Figure 5. Storage of Words, Bytes and Bits in a Byte Organized Memory42
- Table 2. Segment 8 Address Range Mapping43
- Table 3. 512 Kbyte Iflash Memory Block Organization43
- Table 4. 320 Kbyte Xflash Memory Block Organization43
- IRAM and SFR Area44
- The On-Chip XRAM49
  - XRAM Access Via External Masters50
- External Memory Space50
- Crossing Memory Boundaries51
The Central Processing Unit (CPU)52
- Instruction Pipelines54
- Bit-Handling and Bit-Protection59
- Instruction Execution Times60
- CPU Special Function Registers61
Multiply-Accumulate Unit (MAC)82
- MAC Features82
- MAC Operation83
- MAC Register Set91
  - Address Registers91
  - Accumulator & Control Registers91
- MAC Instruction Set Summary94
- Table 13. MAC Register Address in Coreg Addressing Mode94
- Table 14. MAC Instruction Set Summary94
Interrupt and Trap Functions96
- Interrupt System Structure96
- Operation of the PEC Channels104
- Table 17. PEC Control Register Addresses104
- Prioritizing Interrupt & PEC Service Requests106
- Saving the Status During Interrupt Service108
  - Context Switching109
  - Figure 21. Task Status Saved on the System Stack109
- Interrupt Response Times110
- External Interrupts113
  - Table 19. Pins to be Used as External Interrupt Inputs114
  - Fast External Interrupts115
- X-Peripheral Interrupt117
- Table 20. X-Interrupt Detailed Mapping118
- Figure 24. X-Interrupt Basic Structure118
- Trap Functions128
Parallel Ports134
- Introduction134
- Port0139
  - Alternate Functions of PORT0140
  - Figure 28. PORT0 I/O and Alternate Functions141
- Port1142
- Port2146
- Port3150
- Port4154
- Port5161
- Port6164
- Port7169
- Port8172
Dedicated Pins179
- Table 29. Summary of Dedicated Pins179
- Figure 56. RPD External RC Circuit180
The External Bus Interface181
- Single Chip Mode181
- Figure 57. Sfrs and Port Pins Associated with the External Bus Interface182
- External Bus Modes183
- Programmable Bus Characteristics190
- Controlling the External Bus Controller196
- EBC Idle State203
- Table 31. Status of the External Bus Interface During EBC Idle State203
- External Bus Arbitration204
- The XBUS Interface207
- Figure 71. External Bus Arbitration, (Regaining the Bus)207
- Table 32. Definition of XBUS Address Areas208
- Figure 72. Memory Mapping (User Mode: Flash Read Operations / XADRS = 800Bh)210
- Figure 73. Memory Mapping (User Mode: Flash Read Operations / XADRS = C00Ah)211
- EA Functionality213
- Figure 74. EA / VSTBY External Circuit214
The General Purpose Timer Units215
- Timer Block GPT1215
- Timer Block GPT2232
Asynchronous / Synchronous Serial Interface246
- Figure 99. Sfrs and Port Pins Associated with ASC0246
- Asynchronous Operation249
- Figure 100. Asynchronous Mode of Serial Channel ASC0249
- Figure 101. Asynchronous 8-Bit Data Frames250
- Synchronous Operation251
- Figure 102. Asynchronous 9-Bit Data Frames251
- Figure 103. Synchronous Mode of Serial Channel ASC0252
- Hardware Error Detection253
- ASC0 Baud Rate Generation253
- ASC0 Interrupt Control254
- Figure 104. ASC0 Interrupt Generation256
XBUS Asynchronous / Synchronous Serial Interface257
- Figure 105. XBUS Registers and Port Pins Associated with XASC258
- Asynchronous Operation261
- Figure 106. Asynchronous Mode of Serial Channel XASC262
- Figure 107. Asynchronous 8-Bit Data Frames262
- Synchronous Operation264
- Figure 108. Asynchronous 9-Bit Data Frames264
- Figure 109. Synchronous Mode of Serial Channel XASC265
- Hardware Error Detection266
- XASC Baud Rate Generation266
- XASC Interrupt Control267
- Figure 110. XASC Interrupt Generation269
High-Speed Synchronous Serial Interface270
- Figure 111. Sfrs and Port Pins Associated with the SSC271
- Figure 112. Synchronous Serial Channel SSC Block Diagram272
- Full-Duplex Operation275
- Figure 113. Serial Clock Phase and Polarity Options276
- Figure 114. SSC Full Duplex Configuration276
- Half Duplex Operation278
  - Port Control279
  - Figure 115. SSC Half Duplex Configuration279
- Baud Rate Generation280
- Error Detection Mechanisms281
- SSC Interrupt Control282
- Figure 116. SSC Error Interrupt Control282
XBUS High-Speed Synchronous Serial Interface284
- Figure 117. XBUS Registers and Port Pins Associated with the XSSC285
- Figure 118. Synchronous Serial Channel XSSC Block Diagram286
- Full-Duplex Operation290
- Figure 119. Serial Clock Phase and Polarity Options290
- Figure 120. XSSC Full Duplex Configuration291
- Half Duplex Operation293
  - Figure 121. XSSC Half Duplex Configuration293
  - Port Control294
- Baud Rate Generation294
- Error Detection Mechanisms295
- XSSC Interrupt Control296
Watchdog Timer297
- Figure 122. Sfrs and Port Pins Associated with the Watchdog Timer297
- Figure 123. Watchdog Timer Block Diagram297
- Operation of the Watchdog Timer298
- Table 42. WDTCON Bits Value on Different Resets299
- Table 43. WDTREL Reload Value300
- Table 44. Reset Events Summary300
The Bootstrap Loader302
- Selection Among User-Code, Standard or Alternate Bootstrap302
- Standard Bootstrap Loader303
- Standard Bootstrap with UART (RS232 or K-Line)309
- Standard Bootstrap with CAN313
- Comparing the Old and the New Bootstrap Loader319
- Alternate Boot Mode (ABM)320
- Selective Boot Mode323
- Figure 132. Reset Boot Sequence325
The Capture / Compare Units326
- Figure 133. Sfrs and Port Pins Associated with the CAPCOM Units327
- CAPCOM Timers329
- Figure 134. CAPCOM Unit Block Diagram329
- Figure 135. Block Diagram of CAPCOM Timers T0 and T7330
- Figure 136. Block Diagram of CAPCOM Timers T1 and T8330
- CAPCOM Unit Timer Interrupts333
- Capture / Compare Registers333
  - Selection of Capture Modes and Compare Modes335
- Capture Mode336
- Compare Modes336
- Capture / Compare Interrupts343
- Figure 143. Timing Example for Double Register Compare Mode343
- Table 51. CAPCOM Unit Interrupt Control Register Addresses344
Pulse Width Modulation Module345
- Figure 144. Sfrs and Port Pins Associated with the PWM Module346
- Operating Modes347
- PWM Module Registers351
- Figure 149. Operation and Output Waveform in Single Shot Mode351
- Table 52. PWM Frequencies352
- Table 53. PWM Module Channel Specific Register Addresses353
- Interrupt Request Generation354
- PWM Output Signals355
- Figure 150. PWM Output Signal Generation356
XBUS Pulse Width Modulation Module357
- Figure 151. XBUS Registers and Port Pins Associated with the XPWM Module358
- Operating Modes359
- XPWM Module Registers363
- Figure 156. Operation and Output Waveform in Single Shot Mode363
- Table 54. XPWM Frequencies364
- Table 55. XPWM Module Channel Specific Register Addresses365
- Interrupt Request Generation367
- XPWM Output Signals368
- Figure 157. XPWM Output Signal Generation369
Analog / Digital Converter370
- Figure 158. Sfrs, XBUS Registers and Port Pins Associated with the A/D Converter371
- Mode Selection and Operation372
- Conversion Timing Control381
- A/D Converter Interrupt Control382
- Table 56. ADC Sampling and Conversion Timing382
- Calibration383
- A/D Conversion Accuracy383
I 2 C Interface392
- Main Features392
- General Description393
- Functional Description395
- Interrupts400
- Table 57. Interrupt Event Summary401
- Figure 171. Event Flags and Interrupt Generation401
- Register Description403
CAN Modules410
- Memory and Pin Mapping410
- Interrupt413
- Configuration Support413
- Clock Prescaling416
- Figure 174. Connection to Two Different CAN Buses (E.g. for Gateway Application)416
- Figure 175. Connection to One CAN Bus with Internal Parallel Mode Enabled416
- CAN Module: Functional Overview417
- Block Diagram418
- Operating Modes418
- Programmer's Model422
- CAN Application444
Real Time Clock464
- Figure 187. Sfrs Associated with the RTC465
- Figure 188. XBUS Registers Associated with the RTC465
- RTC Registers466
- Programming the RTC470
System Reset472
- Input Filter472
- Asynchronous Reset472
- Table 63. Reset Event Definition472
- Figure 192. Asynchronous Power-On RESET (EA = 1)474
- Figure 193. Asynchronous Power-On RESET (EA = 0)475
- Figure 194. Asynchronous Hardware RESET (EA = 1)476
- Synchronous Reset (Warm Reset)477
- Figure 195. Asynchronous Hardware RESET (EA = 0)477
- Figure 196. Synchronous Short / Long Hardware RESET (EA = 1)480
- Figure 197. Synchronous Short / Long Hardware RESET (EA = 0)481
- Figure 198. Synchronous Long Hardware RESET (EA = 1)482
- Software Reset483
- Figure 199. Synchronous Long Hardware RESET (EA = 0)483
- Watchdog Timer Reset484
- Figure 200. SW / WDT Unidirectional RESET (EA = 1)485
- Bidirectional Reset486
- Figure 201. SW / WDT Unidirectional RESET (EA = 0)486
- Figure 202. SW / WDT Bidirectional RESET(EA = 1)488
- Figure 203. SW / WDT Bidirectional RESET (EA = 0)489
- Reset Circuitry490
- Figure 204. SW / WDT Bidirectional RESET (EA = 0) Followed by a HW RESET490
- Figure 205. Minimum External Reset Circuitry491
- Reset Application Examples492
- Figure 206. System Reset Circuit492
- Figure 207. Example of Software or Watchdog Bidirectional Reset (EA = 1)493
- Figure 208. Example of Software or Watchdog Bidirectional Reset (EA = 0)494
- Reset Summary495
  - Table 64. Reset Events Summary495
  - System Start-Up Configuration496
  - Figure 209. PORT0 Bits Latched into the Different Registers after Reset497
  - Table 65. PORT0 Latched Configuration for the Different Reset Events497
Power Reduction Modes502
- Idle Mode503
- Table 66. Power Reduction Modes Summary503
- Power down Mode504
Programmable Output Clock Divider514
Register Set515
- Register Description Format515
- General Purpose Registers (Gprs)516
- Table 68. General Purpose Registers (Gprs)516
- Table 69. General Purpose Registers (Gprs) Bit Wise Addressing516
- Special Function Registers Ordered by Name517
- Table 70. Special Function Registers Ordered by Name517
- Special Function Registers Ordered by Address524
- Table 71. Special Function Registers Ordered by Address524
- X-Registers Ordered by Name531
- Table 72. X-Registers Ordered by Name531
- X-Registers Ordered by Address536
- Table 73. X-Registers Ordered by Address536
- Flash Registers Ordered by Name541
- Flash Registers Ordered by Address541
- Table 74. Flash Registers Ordered by Name541
- Table 75. Flash Registers Ordered by Address541
- Special Notes542
- Identification Registers543
System Programming545
- Stack Operations547
- Table 76. Stack Size Selection548
- Figure 214. Physical Stack Address Generation549
- Register Banking551
- Procedure Call Entry and Exit551
- Figure 215. Local Registers553
- Peripheral Control and Interface554
- Floating Point Support554
- Trap / Interrupt Entry and Exit554
- Inseparable Instruction Sequences555
- Overriding the DPP Addressing Mechanism555
- Handling the Internal Flash556
- Pits, Traps and Mines558
- Table 77. Document Revision History561

ST ST10F276E - Figure 209. PORT0 Bits Latched into the Different Registers after Reset; Table 65. PORT0 Latched Configuration for the Different Reset Events

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