DocID13284 Rev 2 205/564
UM0404 The external bus interface
DP6.7 = ‘0’) while the other one must be operated in its slave mode (selected with
DP6.7 = ‘1’).
In slave mode the ST10F276 inverts the direction of its HLDA
pin and uses it as an input,
while the master’s HLDA
pin remains an output. This approach does not require any
additional glue logic for the bus arbitration (see Figure 69).
When the bus arbitration is enabled (HLDEN = ‘1’) the three corresponding pins are
automatically controlled by the EBC. Normally the respective port direction register bit retain
their reset value which is ‘0’. This selects master mode where the device operates
compatible with earlier versions. Slave mode is enabled by intentionally switching pin BREQ
to output (DP6.7 = ‘1’) which is neither required for Master Mode nor for earlier devices.
8.6.2 Entering the hold state
Access to the ST10F276’s external bus is requested by driving its HOLD input low. After
synchronizing this signal the ST10F276 will complete a current external bus cycle (if any is
active), release the external bus and grant access to it by driving the HLDA
output low.
During hold state the ST10F276 treats the external bus interface as follows:
• Address and data bus(es) float to tri-state
• ALE is pulled low by an internal pull-down device
• Command lines are pulled high by internal pull-up devices (RD
, WR/WRL, BHE/WRH)
• CSx
outputs are pulled high (push-pull mode) or float to tri-state (open drain mode)
Should the ST10F276 require access to its external bus during hold mode, it activates its
bus request output BREQ
to notify the arbitration circuitry. BREQ is activated only during
hold mode. It will be inactive during normal operation (see Figure 2 on page 24).
Figure 69. Sharing external resources using slave mode
BREQ
HLDA
HOLD
BREQ
HLDA
HOLD
ST10F276
in
ST10F276
in
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