Interrupt and trap functions UM0404
108/564 DocID13284 Rev 2
5.4 Saving the status during interrupt service
Before an interrupt request that has been arbitrated is actually serviced, the status of the
current task is automatically saved on the system stack. The CPU status (PSW) is saved
along with the location where the execution of the interrupted task is to be resumed after
returning from the service routine.
This return location is specified through the Instruction Pointer (IP) and, in case of a
segmented memory model, the Code Segment Pointer (CSP). Bit SGTDIS in register
SYSCON controls how the return location is stored.
The system stack receives the PSW first, followed by the IP (unsegmented) or followed by
CSP and then IP (segmented mode). This optimizes the usage of the system stack, if
segmentation is disabled.
The CPU priority field (ILVL in PSW) is updated with the priority of the interrupt request that
is to be serviced, so the CPU now executes on the new level. If a multiplication or division
was in progress at the time the interrupt request was acknowledged, bit MULIP in register
PSW is set to ‘1’. In this case the return location that is saved on the stack is not the next
instruction in the instruction flow, but rather the multiply or divide instruction itself, as this
instruction has been interrupted and will be completed after returning from the service
routine.
5 XXXX
Interrupt Class 3: 6 sources on 2
levels
4XX
3
2
1
0 No service!
Table 18. Example of software controlled interrupt classes
ILVL (priority)
GLVL
Interpretation
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