ST ST10F276E - ST10 Configuration in CAN BSL; Loading the Start-Up Code Via CAN

DocID13284 Rev 2 315/564
UM0404 The bootstrap loader
15.4.3 ST10 configuration in CAN BSL
When the ST10F276 has entered BSL mode via CAN, the following configuration is
automatically set (values that deviate from the normal reset values, are marked in bold):
Other than after a normal reset the watchdog timer is disabled, so the bootstrap loading
sequence is not time limited. Pin CAN1_TxD1 is configured as output, so the ST10F276 can
return the identification frame. Even if the internal IFlash is enabled, no code can be
executed out of it.
15.4.4 Loading the start-up code via CAN
After sending the acknowledge byte the BSL enters a loop to receive 128 bytes via CAN1.
Hint: the number of bytes loaded when booting via the CAN interface has been extended to
128 bytes in order to allow the re-configuration of the CAN Bit Timing Register with the best
timings (synchronization window, ...). This can be achieved by the following sequence of
instructions:
ReconfigureBaudRate:
MOV R1,#041h
MOV DPP3:0EF00h,R1 ; Put CAN in Init, enable Configuration Change
MOV R1,#01600h
MOV DPP3:0EF06h,R1 ; 1MBaud at Fcpu = 20 MHz
These 128 bytes are stored sequentially into locations 00’FA40
H
through 00’FABF
H
of the
IRAM. So up to 64 instructions may be placed into the RAM area. To execute the loaded
code the BSL then jumps to location 00’FA40
H
, that is, the first loaded instruction. The
bootstrap loading sequence is now terminated, the ST10F276 remains in BSL mode,
however. Most probably the initially loaded routine will load additional code or data, as an
average application is likely to require substantially more than 64 instructions. This second
receive loop may directly use the pre-initialized CAN interface to receive data and store it to
arbitrary user-defined locations.
Watchdog Timer: Disabled
Register SYSCON: 0404
H
(1)
1. In Bootstrap modes (standard or alternate) ROMEN, bit 10 of SYSCON, is always set regardless of EA pin
level. BYTDIS, bit 9 of SYSCON, is set according to data bus width selection via Port0 configuration.
; XPEN bit set
Context Pointer CP: FA00
H
Register STKUN: FA00
H
Stack Pointer SP: FA40
H
Register STKOV: FC00
H
Register BUSCON0: acc. to start-up config.
(2)
2. BUSCON0 is initialized with 0000h, external bus disabled, if pin EA is high during reset. If pin EA is low
during reset, BUSACT0, bit 10, and ALECTL0, bit 9, are set enabling the external bus with lengthened ALE
signal. BTYP field, bit 7 and 6, is set according to Port0 configuration.
CAN1 Status/Control
Register:
0000
H
CAN1 Bit Timing Register: according to ‘0’ frame
Register XPERCON: 042D
H
; XRAM1-2, CAN1, XFlash and XMISC enabled
P4.6 / CAN1_TxD: note
(1)
DP4.6: note
(1)