ST ST10F276E - Interrupt Control Functions in the PSW

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UM0404 Interrupt and trap functions
Note: All requests on levels 13...1 cannot initiate PEC transfers.
They are always serviced by an interrupt service routine. No PECC register is associated
and no COUNT field is checked.
5.1.5 Interrupt control functions in the PSW
The Processor Status word (PSW) is functionally divided into two parts: The lower byte of
the PSW basically represents the arithmetic status of the CPU, the upper byte of the PSW
controls the interrupt system of the ST10F276 and the arbitration mechanism for the
external bus interface.
Note: Pipeline effects have to be considered when enabling/disabling interrupt requests via
modifications of register PSW (see Section 3: The central processing unit (CPU) on
page 52).
PSW (FF10h / 88h) SFR Reset Value: 0000h
CPU Priority ILVL defines the current level for the operation of the CPU. This bit field
reflects the priority level of the routine that is currently executed. Upon the entry into an
interrupt service routine this bit field is updated with the priority level of the request that is
being serviced. The PSW is saved on the system stack before. The CPU level determines
the minimum interrupt priority level that will be serviced. Any request on the same or a lower
level will not be acknowledged.
The current CPU priority level may be adjusted via software to control which interrupt
request sources will be acknowledged.
PEC transfers do not really interrupt the CPU, but rather “steal” a single cycle, so PEC
services do not influence the ILVL field in the PSW.
1514131211109876543210
ILVL IEN
HLD
EN
---USR0
MUL
IP
EZVCN
RW RW RW RW RW RW RW RW RW RW
Bit Function
N, C, V, Z, E,
MULIP, USR0
CPU status flags (Described in “
Section 3: The central processing unit (CPU)
on page 52
”)
Define the current status of the CPU (ALU, Multiplication Unit).
HLDEN
HOLD Enable (Enables External Bus Arbitration)
’0’: Bus arbitration disabled, P6.7...P6.5 may be used for general purpose I/O.
’1’: Bus arbitration enabled, P6.7...P6.5 serve as BREQ
, HLDA, HOLD, respectively.
IEN
Interrupt Enable Control bit (globally enables/disables interrupt requests)
‘0’: Interrupt requests are disabled
‘1’: Interrupt requests are enabled
ILVL
CPU Priority Level
Defines the current priority level for the CPU.
’Fh’: Highest priority level
’0h’: Lowest priority level