ST ST10F276E - Figure 50. Block Diagram of Port7 Pins 3

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UM0404 Parallel ports
Figure 50. Block diagram of Port7 pins 3...0
Pins P7.7...P7.4 (CC31IO...CC28IO) combine internal bus data and alternate data output
before the port latch input, as do the Port2 pins.
Open Drain
Latch
Write ODP7.y
Read ODP7.y
Direction
Latch
Write DP7.y
Read DP7.y
Internal Bus
MUX
0
1
Input
Latch
Clock
P7.y / POUTy
Output
Buffer
y = (3...0)
Port Output
Latch
Read P7.y
Write P7.y
=1
Port Data
Output
XOR
Alternate
Data
Output