ST ST10F276E - Register Description

DocID13284 Rev 2 403/564
UM0404 I
2
C interface
20.5 Register description
I2CCR (EA00h) XBUS Reset Value: 0000h
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
–PEENGCSTARTACKSTOPITE
RW RW RW RW RW RW
Bit Function
ITE
Interrupt Enable
This bit is set and cleared by software and cleared by hardware when the interface
is disabled (PE
= 0).
‘0’: Interrupts disabled.
‘1’: Interrupts enabled.
Refer to Figure 171 for the relationship between the events and the interrupt. SCL is
held low when the ADD10, SB, BTF or ADSL flags or an EV6 event (see Figure 170)
is detected.
STOP
Generation of a Stop condition
This bit is set and cleared by software. It is also cleared by hardware in master
mode. This bit is not cleared when the interface is disabled (PE
= 0).
– In master mode:
‘0’: No stop generation.
‘1’: Stop generation after the current byte transfer or after the current Start
condition is sent. The STOP bit is cleared by hardware when the Stop condition is
sent.
– In slave mode:
‘0’: No stop generation.
‘1’: Release the SCL and SDA lines after the current byte transfer (BTF
= 1). In
this mode the STOP bit has to be cleared by software.
ACK
Acknowledge Enable
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE
= 0).
‘0’: No acknowledge returned
‘1’: Acknowledge returned after an address byte or a data byte is received
START
Generation of a Start condition
This bit is set and cleared by software. It is also cleared by hardware when the
interface is disabled (PE
= 0) or when the Start condition is sent (with interrupt
generation if ITE
= 1).
– In master mode:
‘0’: No start generation.
‘1’: Repeated start generation.
– In slave mode:
‘0’: No start generation.
‘1’: Start generation when the bus is free.