Architectural overview UM0404
28/564 DocID13284 Rev 2
1.2.1 Peripheral event control and interrupt control
The Peripheral Event Controller (PEC) makes it possible to respond to an interrupt request
with a single data transfer (word or byte) which only consumes one instruction cycle and
does not require a save and restore of the machine status.
Each interrupt source is prioritized in every instruction cycle in the interrupt control block. If a
PEC service is selected, a PEC transfer is started. If CPU interrupt service is requested, the
current CPU priority level stored in the PSW register is tested to determine whether a higher
priority interrupt is currently being serviced.
When an interrupt is acknowledged, the current state of the machine is saved on the internal
system stack and the CPU branches to the system specific vector for the peripheral.
The PEC contains a set of SFRs which store the count value and control bit for eight data
transfer channels. In addition, the PEC uses a dedicated area of RAM which contains the
source and destination addresses. The PEC is controlled similarly to any other peripheral
through SFRs containing the desired configuration of each channel.
An individual PEC transfer counter is implicitly decremented for each PEC service except
forming in the continuous transfer mode. When this counter reaches zero, a standard
interrupt is performed to the vector location related to the corresponding source. PEC
services are very well suited, for example, to move register contents to/from a memory
table. The ST10F276 has eight PEC channels each of which offers such fast interrupt-driven
data transfer capabilities.
1.2.2 Memory areas
The memory space of the ST10F276 is organized as a unified memory which means that
code memory, data memory, registers and I/O ports are organized within the same linear
address space which covers up to 16 Mbytes. The entire memory space can be accessed
byte wise or word wise. Particular portions of the on-chip memory have additionally been
made directly bit addressable.
A 2 Kbyte 16-bit wide IRAM provides fast access to General Purpose Registers (GPRs),
user data (variables) and system stack. The IRAM may also be used for code. A unique
decoding scheme provides flexible user register banks in the internal memory while
optimizing the remaining RAM for user data.
The CPU contains an actual register context, consisting of up to 16 word wide and/or byte
wide GPRs which are physically located within the IRAM area.
A Context Pointer (CP) register determines the base address of the active register bank to
be accessed by the CPU at a time. The number of register banks is only restricted by the
available IRAM space. For easy parameter passing, one register bank may overlap others.
A system stack of up to 1024 words is provided as a storage for temporary data. The system
stack is also located within the IRAM area, and it is accessed by the CPU via the stack
pointer (SP) register. Two separate SFRs, STKOV and STKUN, are implicitly compared
against the stack pointer value upon each stack access for the detection of a stack overflow
or underflow.
Hardware detection of the selected memory space is placed at the internal memory
decoders and allows the user to specify any address directly or indirectly and obtain the
desired data without using temporary registers or special instructions.
A 66 Kbyte 16-bit wide on-chip XRAM provides fast access to user data (variables), user
stacks and code. The on-chip XRAM is an X-Peripheral and appears to the software as an
To Next Page
Loading...
