ST ST10F276E - Illegal External Bus Access Trap; Illegal Instruction Access Trap; Illegal Word Operand Access Trap

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UM0404 Interrupt and trap functions
5.8.9 Illegal word operand access trap
Whenever a word operand read or write access is attempted to an odd byte address, the
ILLOPA flag in register TFR is set and the CPU enters the illegal word operand access trap
routine. The IP value pushed onto the system stack is the address of the instruction
following the one which caused the trap.
5.8.10 Illegal instruction access trap
Whenever a branch is made to an odd byte address, the ILLINA flag in register TFR is set
and the CPU enters the illegal instruction access trap routine. The IP value pushed onto the
system stack is the illegal odd target address of the branch instruction.
5.8.11 Illegal external bus access trap
Whenever the CPU requests an external instruction fetch, data read or data write, and no
external bus configuration has been specified, the ILLBUS flag in register TFR is set and the
CPU enters the illegal bus access trap routine. The IP value pushed onto the system stack
is the address of the instruction following the one which caused the trap.