DocID13284 Rev 2 213/564
UM0404 The external bus interface
Note: 1 When CAN1, CAN2, RTC, XASC, XSSC, I
2
C, XPWM and the XBUS Additional Features are
all disabled via XPERCON setting, then any access in the address range 00’E800h -
00’EFFFh will be directed to external memory interface, using the BUSCONx register
corresponding to address matching ADDRSELx register. All pins involved with X-
Peripherals, can be used as General Purpose I/O whenever the related module is not
enabled.
2 The default XPER selection after Reset is identical to XBUS configuration of
ST10F168/ST10F269: CAN1 is enabled, CAN2 is disabled, XRAM1 (2 Kbyte compatible
XRAM) is enabled, XRAM2 (new 64 Kbyte XRAM) is disabled; all the other X-Peripherals
are disabled after Reset.
3 Register XPERCON cannot be changed after the global enabling of X-Peripherals, that is,
after setting of bit XPEN in SYSCON register.
4 In Emulation mode, all the X-Peripherals are enabled (XPERCON bits are all set). It is up to
the bondout chip to redirect or not an access to external memory or to XBUS.
5 Reserved bits of XPERCON register should be always written to ‘0’.
8.8 EA functionality
In ST10F276 the EA pin is shared with V
STBY
supply pin. When main V
DD
is on and stable,
V
STBY
can be temporary grounded: the logic that in Stand-by Mode is powered by V
STBY
(that is 16 Kbyte portion of XRAM, 32 kHz oscillator, Stand-by Voltage Regulator and Real
Time Clock module), is powered by the main V
DD
. This allows to drive low EA pin during
reset as requested to configure the system to start from the external memory.
An appropriate external circuit must be provided to manage dynamically both the
functionalities associated with the pin: during reset and with stable V
DD
, the pin can be tied
low, while after reset (or anyway before turning off the main V
DD
to enter in Stand-by mode)
the V
STBY
supply should be applied.
Refer to Section 24.3: Stand-by mode on page 509 for more details.
XSSCEN
XSSC Enable Bit
‘0’: Accesses to the on-chip XSSC are disabled, external access performed. Address
range 00’E800h-00’E8FFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XI2CEN, XPWMEN and XMISCEN are ‘0’ also.
‘1’: The on-chip XSSC is enabled and can be accessed.
XI2CEN
I
2
C Enable Bit
‘0’: Accesses to the on-chip I
2
C are disabled, external access performed. Address
range 00’EA00h-00’EAFFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XSSCEN, XPWMEN and XMISCEN are ‘0’ also.
‘1’: The on-chip I
2
C is enabled and can be accessed.
XMISCEN
XBUS Additional Features Enable Bit
‘0’: Accesses to the Additional Miscellaneous Features is disabled. Address range
00’EB00h-00’EBFFh is directed to external memory only if CAN1EN, CAN2EN,
XRTCEN, XASCEN, XSSCEN, XPWMEN and XI2CEN are ‘0’ also.
‘1’: The Additional Features are enabled and can be accessed.
Bit Function
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