ST ST10F276E - Port0

DocID13284 Rev 2 139/564
UM0404 Parallel ports
On most of the port lines, the user software is responsible for setting the proper direction
when using an alternate input or output function of a pin.
This is done by setting or clearing the direction control bit DPx.y of the pin before enabling
the alternate function.
There are port lines, however, where the direction of the port line is switched automatically.
For instance, in the multiplexed external bus modes of PORT0, the direction must be
switched several times for an instruction fetch in order to output the addresses and to input
the data.
Obviously, this cannot be done through instructions. In these cases, the direction of the port
line is switched automatically by hardware if the alternate function of such a pin is enabled.
To determine the appropriate level of the port output latches check how the alternate data
output is combined with the respective port latch output.
There is one basic structure for all port lines with only an alternate input function. Port lines
with only an alternate output function, however, have different structures due to the way the
direction of the pin is switched and depending on whether the pin is accessible by the user
software or not in the alternate function mode.
All port lines that are not used for these alternate functions may be used as general purpose
I/O lines. When using port pins for general purpose output, the initial output value should be
written to the port latch prior to enabling the output drivers, in order to avoid undesired
transitions on the output pins. This applies to single pins as well as to pin groups (see
examples below).
Note: When using several BSET pairs to control more pins of one port, these pairs must be
separated by instructions, which do not reference the respective port (see Section 3.1.4:
Particular pipeline effects on page 56).
6.2 PORT0
The two 8-bit ports P0H and P0L represent the higher and lower part of PORT0,
respectively. Both halves of PORT0 can be written (for example via a PEC transfer) without
effecting the other half.
If this port is used for general purpose I/O, the direction of each line can be configured via
the corresponding direction registers DP0H and DP0L.
P0L (FF00h / 80h) SFR Reset Value: - - 00h
SINGLE_Bit: BSET P4.7 ; Initial output level is "high"
BSET DP4.7 ; Switch on the output driver
Bit_GROUP: BFLDH P4, #24H, #24H ; Initial output level is "high"
BFLDH DP4, #24H, #24H ; Switch on the output drivers
1514131211109876543210
- - - - - - - - P0L.7 P0L.6 P0L.5 P0L.4 P0L.3 P0L.2 P0L.1 P0L.0
RW RW RW RW RW RW RW RW