ST ST10F276E - Figure 47. Block Diagram of Port6 Pins 4

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UM0404 Parallel ports
Note: The open drain output option can only be selected via software earliest during the
initialization routine; at least signal CS0
will be in push-pull output driver mode directly after
reset (see Figure 47).
The bus arbitration signals HOLD
, HLDA and BREQ are selected with bit HLDEN in register
PSW. When the bus arbitration signals are enabled via HLDEN, also these pins are
switched automatically to the appropriate direction. Note that the pin drivers for HLDA
and
BREQ
are automatically enabled, while the pin driver for HOLD is automatically disabled
(see Figure 3 on page 30 and Figure 4 on page 41).
Figure 47. Block diagram of Port6 pins 4...0
MUX
0
1
"0"
Open Drain
Latch
Write ODP6.y
Read ODP6.y
Direction
Latch
Write DP6.y
Read DP6.y
Internal Bus
MUX
0
1
Input
Latch
Clock
P6.y
Output
Buffer
y = (4...0)
Port Output
Latch
Read P6.y
Write P6.y
Alternate
Data
Output
MUX
0
1
MUX
0
1
"1"
MUX
Alternate
Function
Enable