DocID13284 Rev 2 275/564
UM0404 High-speed synchronous serial interface
This allows the adaptation of the SSC to a wide range of applications, where serial data
transfer is required.
The data width selection supports the transfer of frames of any length, from 2 bit
“characters” up to 16 bit “characters”. Starting with the LSB (SSCHB = ‘0’) allows
communication with ASC0 devices in synchronous mode like serial interfaces. Starting with
the MSB (SSCHB = ‘1’) allows operation compatible with the SPI interface.
Regardless which data width is selected and whether the MSB or the LSB is transmitted
first, the transfer data is always right aligned in registers SSCTB and SSCRB, with the LSB
of the transfer data in bit 0 of these registers. The data bits are rearranged for transfer by the
internal shift register logic. The unselected bits of SSCTB are ignored, the unselected bits of
SSCRB will be not valid and should be ignored by the receiver service routine.
The clock control allows the adaptation of transmit and receive behavior of the SSC to a
variety of serial interfaces. A specific clock edge (rising or falling) is used to shift out transmit
data, while the other clock edge is used to latch in receive data. Bit SSCPH selects the
leading edge or the trailing edge for each function. Bit SSCPO selects the level of the clock
line in the idle state. So for an idle-high clock the leading edge is a falling one, a 1-to-0
transition. Figure 113 on page 276 is a summary.
12.1 Full-duplex operation
The different devices are connected through three lines. The definition of these lines is
always determined by the master: The line connected to the master's data output pin MTSR
is the transmit line, the receive line is connected to its data input line MRST, and the clock
line is connected to pin SCLK. Only the device selected for master operation generates and
outputs the serial clock on pin SCLK. All slaves receive this clock, so their pin SCLK must
be switched to input mode (DP3.13 = ‘0’). The output of the master’s shift register is
connected to the external transmit line, which in turn is connected to the slaves’ shift register
input.
The output of the slaves’ shift register is connected to the external receive line in order to
enable the master to receive the data shifted out of the slave. The external connections are
hard-wired, the function and direction of these pins is determined by the master or slave
operation of the individual device.
Note: The shift direction shown in the Figure 113 applies for MSB-first operation as well as for
LSB-first operation.
When initializing the devices in this configuration, select one device for master operation
(SSCMS = ‘1’), all others must be programmed for slave operation (SSCMS = ‘0’).
Initialization includes the operating mode of the device's SSC and also the function of the
respective port lines (see Section 12.2.1: Port control on page 279).
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