ST ST10F276E - Programmable Bus Characteristics; ALE Length Control; Figure 61. Programmable External Bus Cycle

The external bus interface UM0404
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8.3 Programmable bus characteristics
Important timing characteristics of the external bus interface have been made user
programmable to allow to adapt it to a wide range of different external bus and memory
configurations with different types of memories and/or peripherals.
The following parameters of an external bus cycle are programmable:
• ALE control defines the ALE signal length and the address hold time after its falling
edge
• Memory cycle time (extendable with 1...15 wait-states) defines the allowable access
time
• Memory tri-state time (extendable with 1 wait-state) defines the time for a data driver
to float
• Read / Write delay time defines when a command is activated after the falling edge of
ALE
• READY polarity is programmable
• READY control defines, if a bus cycle is terminated internally or externally
• Programmable chip select timing control
Note: Internal accesses are executed with maximum speed and therefore are not programmable.
External accesses use the slowest possible bus cycle after reset. The bus cycle timing may
then be optimized by the initialization software.
Figure 61. Programmable external bus cycle
8.3.1 ALE length control
The length of the ALE signal and the address hold time after its falling edge are controlled
by the ALECTLx bit in the BUSCON registers. When bit ALECTL is set to ‘1’, external bus
cycles accessing the respective address window will have their ALE signal prolonged by
half a CPU clock cycle. Also the address hold time after the falling edge of ALE (on a
multiplexed bus) will be prolonged by half a CPU clock, so the data transfer within a bus
ALE
ADDR
RD
/ WR
DATA
ALECTL MCTC MTTC
ALE
ADDR
RD
/ WR
DATA