ST ST10F276E - Figure 113. Serial Clock Phase and Polarity Options; Figure 114. SSC Full Duplex Configuration

High-speed synchronous serial interface UM0404
276/564 DocID13284 Rev 2
Figure 113. Serial clock phase and polarity options
Figure 114. SSC full duplex configuration
Serial Clock
SCLK
Transmit Data
Last
bit
Latch
Data
Shift Data
First
bit
Pins
MTSR / MRST
SSCPO
SSCPH
0
0
1
1
0
1
0
1
Shift Register
MTSR
CLK
MRST
Clock
Master
Device #1
Transmit
Receive
Clock
MTSR
MRST
CLK
Clock
Shift Register
Device #2 Slave
MTSR
MRST
CLK
Clock
Shift Register
Device #2 Slave