ST ST10F276E - Emulation Dedicated Registers; The Processor Status Word PSW

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UM0404 The central processing unit (CPU)
introduced on XBUS for the new ST10 generation. The following instructions must be added
inside the initialization routine:
if (SYSCON.XPEN && (XPERCON & 0x07D3))
then { XPEREMU = XPERCON }
Of course, XPEREMU must be programmed after XPERCON and after SYSCON, in such a
way the final configuration for X-Peripherals is stored in XPEREMU and used for the
emulation hardware setup.
XPEREMU (EB7Eh) XBUS Reset Value: xxxxh
The bit meaning is exactly the same as XPERCON.
3.4.4 Emulation dedicated registers
Four additional registers are implemented for emulation purpose only. Similarly to
XPEREMU, they are write only registers and reserved for emulator software usage. User
should not write to these registers.
XEMU0 (EB76h) XBUS Reset Value: xxxxh
XEMU1 (EB78h) XBUS Reset Value: xxxxh
XEMU2 (EB7Ah) XBUS Reset Value: xxxxh
XEMU3 (EB7Ch) XBUS Reset Value: xxxxh
3.4.5 The processor status word PSW
This bit-addressable register reflects the current state of the microcontroller. Two groups of
bits represent the current ALU status, and the current CPU interrupt status. A separate bit
(USR0) within register PSW is provided as a general purpose user flag.
1514131211109876543210
-----
XMISC
EN
XI2C
EN
XSSC
EN
XASC
EN
XPWM
EN
XFLAS
HEN
XRTC
EN
XRAM2
EN
XRAM1
EN
CAN2
EN
CAN1
EN
WWWWWWWWWWW
1514131211109876543210
XEMU0(15:0)
W
1514131211109876543210
XEMU1(15:0)
W
1514131211109876543210
XEMU2(15:0)
W
1514131211109876543210
XEMU3(15:0)
W