ST ST10F276E - Table 60. C-CAN Register Memory Space Summary

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UM0404 CAN modules
The two sets of interface registers (IF1 and IF2) control the CPU access to the Message
RAM. They buffer the data to be transferred to and from the RAM, avoiding conflicts
between CPU accesses and message reception/transmission.
Table 60. C-CAN register memory space summary
Address Name Reset value Note
CAN Base + 0x00 CAN Control Register 0x0001
CAN Base + 0x02 Status Register 0x0000
CAN Base + 0x04 Error Counter 0x0000 read only
CAN Base + 0x06 Bit Timing Register 0x2301 write enabled by CCE
CAN Base + 0x08 Interrupt Register 0x0000 read only
CAN Base + 0x0A Test Register
0x00 & 0br0000000
(1)
write enabled by Test
CAN Base + 0x0C BRP Extension Register 0x0000 write enabled by CCE
CAN Base + 0x0E — reserved —
(2)
CAN Base + 0x10 IF1 Command Request 0x0001
CAN Base + 0x12 IF1 Command Mask 0x0000
CAN Base + 0x14 IF1 Mask 1 0xFFFF
CAN Base + 0x16 IF1 Mask 2 0xFFFF
CAN Base + 0x18 IF1 Arbitration 1 0x0000
CAN Base + 0x1A IF1 Arbitration 2 0x0000
CAN Base + 0x1C IF1 Message Control 0x0000
CAN Base + 0x1E IF1 Data A 1 0x0000
CAN Base + 0x20 IF1 Data A 2 0x0000
CAN Base + 0x22 IF1 Data B 1 0x0000
CAN Base + 0x24 IF1 Data B 2 0x0000
CAN Base + 0x28 - 0x3E — reserved —
(2)
CAN Base + 0x40 - 0x54 IF2 Registers see note
(3)
same as IF1
Registers
CAN Base + 0x56 - 0x7E — reserved —
(2)
CAN Base + 0x80 Transmission Request 1 0x0000 read only
CAN Base + 0x82 Transmission Request 2 0x0000 read only
CAN Base + 0x84 - 0x8E — reserved —
(2)
CAN Base + 0x90 New Data 1 0x0000 read only
CAN Base + 0x92 New Data 2 0x0000 read only
CAN Base + 0x94 - 0x9E — reserved —
(2)
CAN Base + 0xA0 Interrupt Pending 1 0x0000 read only
CAN Base + 0xA2 Interrupt Pending 2 0x0000 read only
CAN Base + 0xA4 - 0xAE — reserved —
(2)