ST ST10F276E - MAC Register Set; Address Registers; Accumulator & Control Registers

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UM0404 Multiply-accumulate unit (MAC)
The MAC implements ‘2’s complement rounding’. With this rounding type, one is added to
the bit to the right of the rounding point (bit 15 of MAL), before truncation (MAL is cleared).
4.3 MAC register set
4.3.1 Address registers
The new addressing modes require new (E)SFRs: Two address pointers IDX0 / IDX1 and
four offset registers QX0 / QX1 and QR0 / QR1.
IDX0 (FF08h / 84h) SFR Reset Value: 0000h
IDX1 (FF0Ah / 85h) SFR Reset Value: 0000h
QX0 (F000h / 00h) ESFR Reset Value: 0000h
QX1 (F002h / 01h) ESFR Reset Value: 0000h
QR0 (F004h / 02h) ESFR Reset Value: 0000h
QR1 (F006h / 03h) ESFR Reset Value: 0000h
4.3.2 Accumulator & control registers
The MAC unit SFRs include the 40-bit Accumulator (MAL, MAH and the low byte of MSW)
and three control registers: the status word MSW, the control word MCW and the repeat
word MRW.
MAH and MAL are located in the non bit-addressable SFR space.
MAH (FE5Eh / 2Fh) SFR Reset Value: 0000h
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IDXy
RW
Bit Function
IDXy 16-bit IDXy address (y = 0, 1)
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QXz/QRz 0
RW R
Bit Function
QRz/QXz
16-bit address offset for IDXy pointers (QXz) or GPR pointers (QRz).
As MAC instructions handle word operands, bit 0 of these offset registers is
hardwired to ‘0’.
1514131211109876543210
MAH
RW