ST ST10F276E - Oscillator Watchdog (OWD); On-Chip Peripheral Blocks

Architectural overview UM0404
32/564 DocID13284 Rev 2
1.3.4 Oscillator watchdog (OWD)
In order to provide a fail safe mechanism for the instance of a loss of the external clock, an
oscillator watchdog is implemented when the selected clock option is direct drive or direct
drive with prescaler.
The oscillator watchdog operates as follows:
• The Oscillator WatchDog (OWD) is enabled by default after reset. To disable the OWD,
set bit OWDDIS of the SYSCON register.
• When the OWD is enabled, the PLL runs on its free-running frequency, and increments
the Oscillator Watchdog counter.
• On each transition of XTAL1 pin, the Oscillator Watchdog counter is cleared.
If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16
PLL clock cycles). The CPU clock signal will be switched to the PLL clock signal (in this
case, the PLL will run on its basic frequency of 750 kHz to 3 MHz), and the Oscillator
Watchdog Interrupt Request is flagged.
The CPU clock will not switch back to the external clock even if a valid external clock is
applied on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to
external clock input.
When the OWD is disabled, the CPU clock is always fed from the oscillator input and the
PLL is switched off to decrease power supply current.
1.4 On-chip peripheral blocks
The ST10 family of devices separates peripherals from the core. This allows peripherals to
be added or removed without modifications to the core. Each functional block processes
data independently and communicates information over common buses. Peripherals are
controlled by data written to the respective Special Function Registers (SFRs). These SFRs
are located either within the standard SFR area (00’FE00h...00’FFFFh), or within the
extended ESFR area (00’F000h...00’F1FFh).
The built in peripherals are used for interfacing the CPU to the external world, or to provide
on-chip functions. The ST10F276 generic peripherals are:
• Nine I/O ports with a total of 111 I/O lines,
• Two Serial Interfaces (ASC0 and SSC),
• Two General Purpose Timer Blocks (GPT1 and GPT2),
• A Watchdog Timer,
• Two 16-channel Capture / Compare units (CAPCOM1 and CAPCOM2),
• A 4-channel Pulse Width Modulation unit (PWM),
• A 10-bit Analog / Digital Converter.
Each peripheral also contains a set of Special Function Registers (SFRs), which control the
functionality of the peripheral and temporarily store intermediate data results. Each
peripheral has an associated set of status flags. Individually selected clock signals are
generated for each peripheral from binary multiples of the CPU clock.