The external bus interface UM0404
204/564 DocID13284 Rev 2
8.6 External bus arbitration
In high performance systems it may be efficient to share external resources like memory
banks or peripheral devices among more than one controller. The ST10F276 supports this
approach with the possibility to arbitrate the access to its external bus, and to the external
devices.
This bus arbitration allows an external master to request the ST10F276’s bus via the HOLD
input. The ST10F276 acknowledges this request via the HLDA
output and will float its bus
lines in this case. The CS
outputs provide internal pull-up devices.
The new master may now access the peripheral devices or memory banks via the same
interface lines as the ST10F276. During this time the ST10F276 can keep on executing, as
long as it does not need access to the external bus. All actions that just require internal
resources like instruction or data memory and on-chip peripherals, may be executed in
parallel.
When the ST10F276 needs access to its external bus while it is occupied by another bus
master, it demands it via the BREQ
output.
The external bus arbitration is enabled by setting (to ‘1’) bit HLDEN in register PSW. In this
case the three bus arbitration pins HOLD
, HLDA and BREQ are automatically controlled by
the EBC independent of their I/O configuration. This is not true when XSSC is enabled
(setting bit XSSCEN in XPERCON register): the functions HLDA
and BREQ are masked,
and the related pins are controlled by the XSSCPORT register. Bit HLDEN may be cleared
during the execution of program sequences, where the external resources are required but
cannot be shared with other bus masters. In this case the ST10F276 will not answer to
HOLD
requests from other external masters. If HLDEN is cleared while the ST10F276 is in
hold state (code execution from IRAM/IFlash): this hold state is left only after HOLD
has
been deactivated again. In this case the current hold state continues and only the next
HOLD
request is not answered.
Connecting two ST10F276’s in this way would require additional logic to combine the
respective output signals HLDA
and BREQ. This can be avoided by switching one of the
controllers into slave mode where pin HLDA
is switched to input.
This allows to directly connect the slave controller to another master controller without glue
logic. The slave mode is selected by setting bit DP6.7 to’1’. DP6.7 = ‘0’ (default after reset)
selects the Master Mode.
Note: The pins HOLD
, HLDA and BREQ keep their alternate function (bus arbitration) even after
the arbitration mechanism has been switched off by clearing HLDEN.
All three pins are used for bus arbitration after bit HLDEN was set once.
8.6.1 Connecting bus masters
When multiple ST10F276’s or a ST10F276 and another bus master should share external
resources some glue logic is required that defines the currently active bus master and also
enables a ST10F276 which has surrendered its bus interface to regain control of it in case it
must access the shared external resources.
This glue logic is required if the other bus master does not automatically remove its hold
request after having used the shared resources.
When two ST10F276 are connected in this way the external glue logic can be left out. In this
case one of the controllers must be operated in its master mode (default after reset,
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