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UM0404 The central processing unit (CPU)
3.4.7 The code segment pointer CSP
This non-bit-addressable register selects the code segment being used at run-time to
access instructions. The lower 8 bits of register CSP select one of up to 256 segments of 64
Kbytes each, while the upper 8 bits are reserved for future use.
CSP (FE08h / 04h) SFR Reset Value: 0000h
Figure 12. Addressing via the code segment pointer
Note: When segmentation is disabled, the IP value is used directly as the 16-bit address.
Code memory addresses are generated by directly extending the 16-bit contents of the IP
register by the contents of the CSP register as shown in the Figure 1 on page 23.
In case of the segmented memory mode the selected number of segment address bits
(7...0, 3...0 or 1...0) of register CSP is output on the segment address pins A23...A16 of
Port4 for all external code accesses. For non-segmented memory mode the content of this
register is not significant, because all code accesses are automatically restricted to
segment 0.
Bit Function
IP
Instruction Pointer
Specifies the intra segment offset, from where the current instruction is to be fetched. IP
refers to the current segment (SEGNR bit field of CSP register).
1514131211109876543210
-------- SEGNR
R
Bit Function
SEGNR
Segment Number
Specifies the code segment, from where the current instruction is to be fetched. SEGNR
is ignored, when segmentation is disabled.
Code Segment
255
254
1
0
FF’FFFFh
FE’0000h
01’0000h
00’0000h
15 0
CSP Register
15 0
IP Register
24 / 20 / 18-bit Physical Code Address
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