CAN modules UM0404
452/564 DocID13284 Rev 2
The interrupt identifier IntId in the Interrupt Register indicates the cause of the interrupt.
When no interrupt is pending, the register will hold the value zero. If the value of the
Interrupt Register is different from zero, then there is an interrupt pending and, if IE is set,
the interrupt line to the CPU, IRQ_B, is active. The interrupt line remains active until the
Interrupt Register is back to value zero (the cause of the interrupt is reset) or until IE is reset.
The value 0x8000h indicates that an interrupt is pending because the CAN Core has
updated (not necessarily changed) the Status Register (Error Interrupt or Status Interrupt).
This interrupt has the highest priority. The CPU can update (reset) the status bits RxOk,
TxOk and LEC, but a write access of the CPU to the Status Register can never generate or
reset an interrupt.
All other values indicate that the source of the interrupt is one of the Message Objects, IntId
points to the pending message interrupt with the highest interrupt priority.
The CPU controls whether a change of the Status Register may cause an interrupt (bits EIE
and SIE in the CAN Control Register) and whether the interrupt line becomes active when
the Interrupt Register is different from zero (bit IE in the CAN Control Register). The
Interrupt Register will be updated even when IE is reset.
The CPU has two possibilities to follow the source of a message interrupt. First it can follow
the IntId in the Interrupt Register and second it can poll the Interrupt Pending Register (see
Interrupt pending registers on page 443).
An interrupt service routine reading the message that is the source of the interrupt may read
the message and reset the Message Object’s IntPnd at the same time (bit ClrIntPnd in the
Command Mask Register). When IntPnd is cleared, the Interrupt Register will point to the
next Message Object with a pending interrupt.
21.9.10 Configuration of the bit timing
Even if minor errors in the configuration of the CAN bit timing do not result in immediate
failure, the performance of a CAN network can be reduced significantly.
In many cases, the CAN bit synchronization will amend a faulty configuration of the CAN bit
timing to such a degree that only occasionally an error frame is generated. In the case of
arbitration however, when two or more CAN nodes simultaneously try to transmit a frame, a
misplaced sample point may cause one of the transmitters to become error passive.
The analysis of such sporadic errors requires a detailed knowledge of the CAN bit
synchronization inside a CAN node and of the CAN nodes’ interaction on the CAN bus.
Bit time and bitrate
CAN supports bitrates in the range of lower than 1 Kbit/s up to 1000 Kbit/s. Each member of
the CAN network has its own clock generator, usually a quartz oscillator. The timing
parameter of the bit time (that is, the reciprocal of the bitrate) can be configured individually
for each CAN node, creating a common bitrate even though the CAN nodes’ oscillator
periods (f
osc
) may be different.
The frequencies of these oscillators (or PLL’s when used to generate the CAN clock starting
from a reference obtained through a quartz oscillator) are not absolutely stable, small
variations are caused by changes in temperature or voltage and by deteriorating
components. As long as the variations remain inside a specific oscillator tolerance range
(df), the CAN nodes are able to compensate for the different bitrates by resynchronizing to
the bit stream.
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