ST ST10F276E - Figure 105. XBUS Registers and Port Pins Associated with XASC

XBUS asynchronous / synchronous serial interface UM0404
258/564 DocID13284 Rev 2
Figure 105. XBUS registers and port pins associated with XASC
The operating mode of the serial channels XASC is controlled by its control register
XS1CON. Being an XBUS register, it is not bit-addressable: for this reason, a couple of
additional XBUS registers are provided to set and clear single bits of XS1CON emulating
the bit-addressability (see XS1CONSET, XS1CONCLR. This register contains control bits
for mode and error check selection, and status flags for error identification.
XS1CON (E900h) XBUS Reset Value: 0000h
Ports & Direction Control Alternate Functions Data Registers
15
-
14
-
13
-
12
-
11
-
10
-
9
-
8
-
7
-
6
-
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXS1PORT XS1BG
15
-
14
-
13
-
12
Y
11
Y
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
Y
XS1TBUF - - - -
- - - YYYYYYYYY
XS1RBUF - - - -
- - - YYYYYYYYY
Control Registers Interrupt Control
15
Y
14
Y
13
Y
12
Y
11
-
10
Y
9
Y
8
Y
7
Y
6
Y
5
Y
4
Y
3
Y
2
Y
1
Y
0
YXS1CON
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XIRxSEL
YYYY
Y Y YYYYYYYYYYXIRxSET
YYYY
Y Y YYYYYYYYYYXIRxCLR
YYYY
Y Y YYYYYYYYYY
RXD1 / P8.6
TXD1 / P8.7
XS1PORT XASC Port Control Register
XS1BG XASC Baud rate Generator/Reload Register
XS1CON XASC Control Register
XS1CONSET XASC Control Register bit set (write only)
XS1CONCLR XASC Control Register bit clear (write only)
XS1TBUF XASC Transmit Buffer Register
XS1RBUFXASC Receive Buffer Register (read only)
XIRxSEL XPxINT Interrupt Selection Control Register
XIRxSET XPxINT Interrupt Selection Control Reg. Bit Set
XIRxCLR XPxINT Interrupt Selection Control Reg. Bit Clear
Bit is linked to a function
Bit has no function or is not implemented
Y
-
:
:
YYYY - Y YYYYYYYYYYXS1CONSET
YYYY
- Y YYYYYYYYYYXS1CONCLR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
S1R S1LB S1BRS S1ODD - S1OE S1FE S1PE S1OEN S1FEN S1PEN S1REN S1STP S1M
RW RW RW RW RW RW RW RW RW RW RW RW RW