ST ST10F276E - Figure 170. Transfer Sequencing

DocID13284 Rev 2 399/564
UM0404 I
2
C interface
Figure 170. Transfer sequencing
Legend:
7-bit Slave receiver:
7-bit Slave transmitter:
7-bit Master receiver:
7-bit Master transmitter:
10-bit Slave receiver:
10-bit Slave transmitter
:
10-bit Master transmitter:
10-bit Master receiver:
S Address A Data1 A Data2 A
.....
DataN A P
EV1 EV2 EV2 EV2 EV4
S Address A Data1 A Data2 A
.....
DataN NA P
EV1 EV3 EV3 EV3 EV3-1 EV4
S Address A Data1 A Data2 A
.....
DataN NA P
EV5 EV6 EV7 EV7 EV7
S Address A Data1 A Data2 A
.....
DataN A P
EV5 EV6 EV8 EV8 EV8 EV8
S Header A Address A Data1 A
.....
DataN A P
EV1 EV2 EV2 EV4
S
r
Header A Data1 A
.....
DataN A P
EV1 EV3 EV3 EV3-1 EV4
S Header A Address A Data1 A
.....
DataN A P
EV5 EV9 EV6 EV8 EV8 EV8
S
r
Header A Data1 A
.....
DataN A P
EV5 EV6 EV7 EV7
S Start
S
r
Repeated Start
P Stop
A Acknowledge
NA Non-acknowledge
EVx Event (with interrupt if ITE
= 1)
EV1 EVF
= 1, ADSL = 1, cleared by reading I2CSR1 register.
EV2 EVF = 1, BTF = 1, cleared by reading I2CDR register.
EV3 EVF
= 1, BTF = 1, cleared by reading I2CSR1 register followed by writing I2CDR register.