ST ST10F276E - Page 398

I
2
C interface UM0404
398/564 DocID13284 Rev 2
Master receiver
Following the address transmission and after I2CSR1 and I2CCR registers have been
accessed, the master receives bytes from the SDA line into the I2CDR register via the
internal shift register. After each byte the interface generates in sequence:
• Acknowledge pulse if the ACK bit is set
• EVF and BTF bits are set by hardware with an interrupt if the ITE bit is set.
Then the interface waits for a read of the I2CDR register, holding the SCL line low (see
Figure 170 Transfer sequencing EV7).
To close the communication: before reading the last byte from the I2CDR register, set the
STOP bit to generate the Stop condition. The interface goes automatically back to slave
mode (M/SL bit cleared).
Note: In order to generate the non-acknowledge pulse after the last received data byte, the ACK
bit must be cleared just before reading the second last data byte.
Master transmitter
Following the address transmission and after I2CSR1 register has been read, the master
sends bytes from the I2CDR register to the SDA line via the internal shift register.
The master waits for a write in the I2CDR register, holding the SCL line low (see
Figure 170 - Transfer sequencing EV8).
When the acknowledge bit is received, the interface sets:
• EVF and BTF bits with an interrupt if the ITE bit is set.
To close the communication: after writing the last byte to the I2CDR register, set the STOP
bit to generate the Stop condition. The interface goes automatically back to slave mode
(M/SL bit cleared).