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UM0404 Power reduction modes
from ST10F276 Core (active low signal) is low enough to be recognized as a logic “0” by the
RAM interface (due to V
18
lower than V
18SB
): the bus status could contain a valid address
for the RAM and an unwanted data corruption could occur. For this reason, an extra
interface, powered by the switched supply, is used to prevent the RAM from this kind of
potential corruption mechanism.
WARNING:
During Power-Off phase, it is important that the external hardware maintains a stable
ground level on RSTIN
pin, without any glitch, in order to avoid spurious exiting from reset
status with unstable power supply.
24.3.2 Exiting stand-by mode
After the system has entered the Stand-by Mode, the procedure to exit this mode consists of
a standard Power-On sequence, with the only difference that the RAM is already powered
through V
18SB
internal reference (derived from V
STBY
pin external voltage).
It is recommended to held the device under RESET (RSTIN
pin forced low) until external
V
DD
voltage pin is stable. Even though, at the very beginning of the Power-On phase, the
device is maintained under reset by the internal low voltage detector circuit (implemented
inside the main voltage regulator) till the internal V
18
becomes higher than about 1.0V, there
is no warranty that the device stays under reset status if RSTIN
is at high level during
power ramp up. So, it is important the external hardware is able to guarantee a stable
ground level on RSTIN
along the Power-On phase, without any temporary glitch.
The external hardware should be responsible to drive low the RSTIN
pin until the V
DD
is
stable, even though the internal LVD is active. Besides, it is requested an additional time (at
least 1ms) to allow internal voltage regulator stabilization before releasing the RSTIN
pin:
this is necessary since the internal Flash has to begin its initialization phase (starting when
RSTIN
pin is released) with an already stable V
18
.
Once the internal Reset signal goes low, the RAM (still frozen) power supply is switched to
the main V
18
.
At this time, everything becomes stable, and the execution of the initialization routines can
start: XRAM2EN bit can be set, enabling the RAM.
24.3.3 Real time clock and stand-by mode
When Stand-by mode is entered (turning off the main supply V
DD
), the Real Time Clock
counting can be maintained running in case the on-chip low-power oscillator is used to
provide the reference to the counter. This is not possible if the main oscillator is used as
reference for the counter: being the main oscillator powered by V
DD
, once this is switched
off, the oscillator is stopped.
24.4 Output pin status
During idle mode the CPU clocks are turned off, while all peripherals continue their
operation in the normal way. Therefore all ports pins, which are configured as general
purpose output pins, output the last data value which was written to their port output latches.
If the alternate output function of a port pin is used by a peripheral, the state of the pin is
determined by the operation of the peripheral. Port pins which are used for bus control
functions go into that state which represents the inactive state of the respective function
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