The external bus interface UM0404
188/564 DocID13284 Rev 2
accessible address space. The number of segment address lines is selected during reset
and coded in bit-field SALSEL in register RP0H (see table below).
Note: The total accessible address space may be increased by accessing several banks which
are distinguished by individual chip select signals.
8.2.7 CS signal generation
During external accesses the EBC can generate a (programmable) number of CS lines on
Port6, which allows to directly select external peripherals or memory banks without requiring
an external decoder. The number of CS
lines is selected during reset and coded in bit field
CSSEL in register RP0H (see table below)
The CS outputs are associated with the BUSCONx registers and are driven active (low) for
any access within the address area defined for the respective BUSCON register.
For any access outside this defined address area the respective CS
signal will go inactive
(high). At the beginning of each external bus cycle the corresponding valid CS
signal is
determined and activated. All other CS
lines are deactivated (driven high) at the same time.
Note: The CS
signals will not be updated for an access to any internal address area (for example
when no external bus cycle is started), even if this area is covered by the respective
ADDRSELx register. An access to an on-chip X-Peripheral deactivates all external CS
signals. Upon accesses to address windows without a selected CS
line all selected CS lines
are deactivated.
The chip select signals allow to operate in four different modes, which are selected via bit
CSWENx and CSRENx in the respective BUSCONx register.
SALSEL Segment address lines Directly accessible address space
1 1 Two: A17...A16
256 Kbytes (Default without pull-downs on
P0)
1 0 Eight: A23...A16 16 Mbytes (Maximum)
0 1 None 64 Kbytes (Minimum)
0 0 Four: A19...A16 1 Mbyte
CSSEL Chip select lines Note
1 1 Five: CS4
...CS0 Default without pull-downs on P0
1 0 None Port6 pins free for I/O
0 1 Two: CS1
...CS0
0 0 Three: CS2...CS0
CSWENx CSRENx Chip select mode
0 0 Address Chip Select (Default after Reset, mode for CS0)
0 1 Read Chip Select
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