ST ST10F276E - Interrupts

I
2
C interface UM0404
400/564 DocID13284 Rev 2
Error cases
• BERR: Detection of a Stop or a Start condition during a byte transfer. In this case, the
EVF and BERR bits are set by hardware with an interrupt if ITE is set.
• AF: Detection of a non-acknowledge bit. In this case, the EVF and AF bits are set by
hardware with an interrupt if the ITE bit is set. To resume, set the START or STOP bit.
• ARLO: Detection of an arbitration lost condition or misplaced data transition during
high phase of SCL.
In these cases the ARLO bit is set by hardware (with an interrupt if the ITE bit is set)
and the interface goes automatically back to slave mode (the M/SL bit is cleared).
Note: In all these cases, the SCL line is not held low; however, the SDA line can remain low due to
possible «0» bits transmitted last. It is then necessary to release both lines by software.
20.4 Interrupts
There are three different types of interrupt that the module can generate:
• requests related to bus events, like start or stop events, arbitration lost, etc.;
• requests related to data transmission;
• requests related to data reception;
These requests are issued to the interrupt controller by three different lines, and identified
as Error, Transmit and Receive interrupt lines.
EV3-1 EVF = 1, AF = 1, BTF = 1; AF is cleared by reading I2CSR2 register. BTF is cleared by
releasing the lines (STOP = 1, STOP = 0) or by writing I2CDR register (I2CDR = FFh).
Note: If lines are released by STOP = 1, STOP = 0, the subsequent EV4 is not seen.
EV4 EVF = 1, STOPF = 1, cleared by reading I2CSR2 register.
EV5 EVF
= 1, SB = 1, cleared by reading I2CSR1 register followed by writing I2CDR register.
EV6
EVF = 1, ENDAD = 1, cleared by reading I2CSR2 register followed by writing I2CCR
register (for example PE
= 1).
EV7 EVF
= 1, BTF = 1, cleared by reading I2CDR register.
EV8 EVF = 1, BTF = 1, cleared by writing I2CDR register.
EV9
EVF
= 1, ADD10 = 1, cleared by reading I2CSR1 register followed by writing I2CDR
register.