Architectural overview UM0404
22/564 DocID13284 Rev 2
1 Architectural overview
ST10F276 architecture combines the advantages of both RISC and CISC processors with
an advanced peripheral subsystem. The following block diagram gives an overview of the
different on-chip components and of the advanced, high bandwidth internal bus structure of
the ST10F276 (see Figure 1).
1.1 Basic CPU concepts and optimization
The main core of the CPU includes a 4-stage instruction pipeline, a 16-bit arithmetic and
logic unit (ALU) and dedicated SFRs.
Additional hardware is provided for a separate multiply and divide unit, a bit-mask generator
and a barrel shifter (see Figure 2).
Several areas of the processor core have been optimized for performance and flexibility.
Functional blocks in the CPU core are controlled by signals from the instruction decode
logic. The core improvements are summarized below, and described in detail in the
following sections:
1. High instruction bandwidth / fast execution
2. High function 8-bit and 16-bit arithmetic and logic unit
3. Extended bit processing and peripheral control
4. High performance branch, call and loop processing
5. Consistent and optimized instruction formats
6. Programmable multiple priority interrupt structure
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