ST ST10F276E - Page 21

DocID13284 Rev 2 21/564
UM0404 List of figures
Figure 205. Minimum external reset circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 491
Figure 206. System reset circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 492
Figure 207. Example of software or watchdog bidirectional reset (EA = 1) . . . . . . . . . . . . . . . . . . . . . 493
Figure 208. Example of software or watchdog bidirectional reset (EA = 0) . . . . . . . . . . . . . . . . . . . . . 494
Figure 209. PORT0 bits latched into the different registers after reset . . . . . . . . . . . . . . . . . . . . . . . . 497
Figure 210. Transitions between Idle mode and active mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 504
Figure 211. RPD pin: external circuit to exit power down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 507
Figure 212. Simplified power down exit circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 508
Figure 213. Power down exit sequence using an external interrupt (PLL x 2) real time clock and power
down mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 509
Figure 214. Physical stack address generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 549
Figure 215. Local registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 553