ST ST10F276E - Figure 19. Priority Levels and PEC Channels

Interrupt and trap functions UM0404
102/564 DocID13284 Rev 2
Note: Priority level 0000b is the default level of the CPU. Therefore a request on level 0 will never
be serviced, because it can never interrupt the CPU. However, an enabled interrupt request
on level 0000b will terminate the ST10F276’s Idle mode and reactivate the CPU.
For interrupt requests which are to be serviced by the PEC, the associated PEC channel
number is derived from the respective ILVL (LSB) and GLVL (see Figure 19). So
programming a source to priority level 15 (ILVL = 1111b) selects the PEC channel group
7...4, programming a source to priority level 14 (ILVL = 1110b) selects the PEC channel
group 3...0. The actual PEC channel number is then determined by the group priority field
GLVL (see again Figure 19).
Simultaneous requests for PEC channels are prioritized according to the PEC channel
number, where channel 0 has lowest and channel 8 has highest priority.
All sources that request PEC service must be programmed to different PEC channels.
Otherwise an incorrect PEC channel may be activated.
Figure 19. Priority levels and PEC channels
The table below shows in a few examples, which action is executed with a given
programming of an interrupt control register.
Priority level Type of service
ILVL GLVL COUNT = 00h COUNT ≠ 00h
1 1 1 1 1 1
CPU interrupt, level 15, group
priority 3
PEC service, channel 7
1 1 1 1 1 0
CPU interrupt, level 15, group
priority 2
PEC service, channel 6
1 1 1 0 1 0
CPU interrupt, level 14, group
priority 2
PEC service, channel 2
1 1 0 1 1 0
CPU interrupt, level 13, group
priority 2
CPU interrupt, level 13, group
priority 2
0 0 0 1 1 1
CPU interrupt, level 1, group
priority 3
CPU interrupt, level 1, group
priority 3
0 0 0 1 0 0
CPU interrupt, level 1, group
priority 0
CPU interrupt, level 1, group
priority 0
0 0 0 0 X X No service! No service!
012345
Interrupt
Control Register
PEC Control
ILVL GLVL
PEC Channel #
012