System programming UM0404
554/564 DocID13284 Rev 2
27.5 Peripheral control and interface
All communication between peripherals and the CPU is performed either by PEC transfers
to and from internal memory, or by explicitly addressing the SFRs associated with the
specific peripherals. After resetting the ST10F276 all peripherals (except the watchdog
timer) are disabled and initialized to default values. A desired configuration of a specific
peripheral is programmed using MOV instructions of either constants or memory values to
specific SFRs. Specific control flags may also be altered via bit instructions.
Once in operation, the peripheral operates autonomously until an end condition is reached
at which time it requests a PEC transfer or requests CPU servicing through an interrupt
routine. Information may also be polled from peripherals through read accesses to SFRs or
bit operations including branch tests on specific control bit in SFRs. To ensure proper
allocation of peripherals among multiple tasks, a portion of the internal memory has been
made bit addressable to allow user semaphores. Instructions have also been provided to
lock out tasks via software by setting or clearing user specific bit and conditionally branching
based on these specific bit.
It is recommended that bit-fields in control SFRs are updated using the BFLDH and BFLDL
instructions or a MOV instruction to avoid undesired intermediate modes of operation which
can occur, when BCLR/BSET or AND/OR instruction sequences are used.
27.6 Floating point support
All floating point operations are performed using software. Standard multiple precision
instructions are used to perform calculations on data types that exceed the size of the ALU.
Multiple bit rotate and logic instructions allow easy masking and extracting of portions of
floating point numbers.
To decrease the time required to perform floating point operations, two hardware features
have been implemented in the CPU core. First, the PRIOR instruction aids in normalizing
floating point numbers by indicating the position of the first set bit in a GPR. This result can
the be used to rotate the floating point result accordingly.
The second feature aids in properly rounding the result of normalized floating point numbers
through the overflow (V) flag in the PSW. This flag is set when a one is shifted out of the
carry bit during shift right operations. The overflow flag and the carry flag are then used to
round the floating point result based on the desired rounding algorithm.
27.7 Trap / interrupt entry and exit
Interrupt routines are entered when a requesting interrupt has a priority higher than the
current CPU priority level. Traps are entered regardless of the current CPU priority. When
either a trap or interrupt routine is entered, the state of the machine is preserved on the
system stack and a branch to the appropriate trap/interrupt vector is made.
All trap and interrupt routines require the use of the RETI (return from interrupt) instruction
to exit from the called routine.
This instruction restores the system state from the system stack and then branches back to
the location where the trap or interrupt occurred.
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