The general purpose timer units UM0404
232/564 DocID13284 Rev 2
9.2 Timer block GPT2
From a programmer's point of view, the GPT2 block is represented by a set of SFRs. The
I/O of port and direction registers which are used for alternate functions by the GPT2 block
are noted ‘Y’ in Figure 1 on page 23.
Timer block GPT2 supports high precision event control with a maximum resolution of four
CPU clock cycles. It includes the two timers T5 and T6, and the 16-bit capture/reload
register CAPREL. Timer T6 is referred to as the core timer, and T5 is referred to as the
auxiliary timer of GPT2.
Each timer has an alternate associated input pin which serves as the gate control in gated
timer mode, or as the count input in counter mode. The count direction (Up / Down) may be
programmed via software or may be dynamically altered by a signal at an external control
input pin. An overflow/underflow of T6 is indicated by the output toggle bit T6OTL whose
state may be output on an alternate function port pin. In addition, T6 may be reloaded with
the contents of CAPREL.
The toggle bit also supports the concatenation of T6 with auxiliary timer T5, while
concatenation of T6 with the timers of the CAPCOM units is provided through a direct
connection.
Triggered by an external signal, the contents of T5 can be captured into register CAPREL,
and T5 may optionally be cleared. Both timer T6 and T5 can count up or down, and the
current timer value can be read or modified by the CPU in the non bit-addressable SFRs T5
and T6.
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