ST ST10F276E - XASC Interrupt Control

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UM0404 XBUS asynchronous / synchronous serial interface
An auto-reload of the timer with the content of the reload register is performed each time
XS1BG is written to. However, if S1R = ‘0’ at the time the write operation to XS1BG is
performed, the timer will not be reloaded until the first instruction cycle after S1R = ‘1’.
XS1BG (E906h) XBUS Reset Value: 0000h
Asynchronous mode baud rates
For asynchronous operation, the Baud rate generator provides a clock with 16 times the rate
of the established Baud rate. Every received bit is sampled at the 7th, 8th and 9th cycle of
this clock. The Baud rate for asynchronous operation of serial channel XASC and the
required reload value for a given Baud rate can be determined by the following formulas:
(S1BRL) represents the content of the reload register, taken as unsigned 13-bit integer,
(S1BRS) represents the value of bit S1BRS (‘0’ or ‘1’), taken as integer.
Using the above equation, the maximum Baudrate can be calculated for any given clock
speed. The device datasheet gives a table of values for Baudrate vs. reload register value
for S1BRS = 0 and S1BRS = 1.
Synchronous mode baud rates
For synchronous operation, the Baud rate generator provides a clock with four times the
rate of the established Baud rate. The Baud rate for synchronous operation of serial channel
XASC can be determined by the following formula:
(S1BRL) represents the content of the reload register, taken as unsigned 13-bit integers,
(S1BRS) represents the value of bit S1BRS (‘0’ or ‘1’), taken as integer.
Using the above equation, the maximum Baud rate can be calculated for any given clock
speed.
11.5 XASC interrupt control
Up to four interrupt control registers (XIRxSEL, x = 0, 1, 2, 3) are provided in order to select
the source of the XBUS interrupt: the transmit interrupt, the transmit buffer interrupt, the
receive interrupt and the error interrupt of serial channel XASC are linked to one of the
1514131211109876543210
- - - Baud Rate
RW
B
Async
=
f
CPU
16 x [2 + (S1BRS)] x [(S1BRL) + 1]
S1BRL = (
f
CPU
16 x [2 + (S1BRS)] x B
Async
) - 1
B
Sync
=
S1BRL = (
f
CPU
4 x [2 + (S1BRS)] x B
Sync
) - 1
f
CPU
4 x [2 + (S1BRS)] x [(S1BRL) + 1]