ST ST10F276E - Figure 95. Concatenation of Core Timer T6 and Auxiliary Timer T5; Figure 96. GPT2 Register CAPREL in Capture Mode

The general purpose timer units UM0404
242/564 DocID13284 Rev 2
Figure 95. Concatenation of core timer T6 and auxiliary timer T5
Note: Line only affected by over/underflows of T6, but NOT by software modifications of T6OTL.
Figure 96. GPT2 register CAPREL in capture mode
GPT2 capture / reload register CAPREL in reload mode
This 16-bit register can be used as a reload register for the core timer T6. This mode is
selected by setting bit T6SR = ‘1’ in register T6CON. The event causing a reload in this
mode is an overflow or underflow of the core timer T6.
When timer T6 overflows from FFFFh to 0000h or when it underflows from 0000h to FFFFh,
the value stored in register CAPREL is loaded into timer T6. This will not set the interrupt
request flag CRIR associated with the CAPREL register. However, interrupt request flag
T6IR will be set indicating the overflow/underflow of T6.
T5l
T5R
Auxiliary Timer T5
T5IR
Interrupt
Request
T6OTL
Edge
Select
T6OE
T6IR
Interrupt
1)
Core Timer T6
T6R
Up/Down
X
T6l
CPU
Clock
T6OUT
Request
P3.1
Cl
Edge
Select
T5CLR
CAPIN
P3.2
T5SC
Auxiliary Timer T5
CAPREL Register
CRIR
T5IR
Interrupt
Request
Interrupt
Request
Up/Down
Input
Clock
T3IN
P3.6
T3EUD
P3.4