DocID13284 Rev 2 241/564
UM0404 The general purpose timer units
T6OTL is selected to clock the auxiliary timer, this concatenation forms a 32-bit or a 33-bit
timer / counter.
• 32-bit Timer/Counter: If both a positive and a negative transition of T6OTL is used to
clock the auxiliary timer, this timer is clocked on every overflow/underflow of the core
timer T6. Thus, the two timers form a 32-bit timer.
• 33-bit Timer/Counter: If either a positive or a negative transition of T6OTL is selected to
clock the auxiliary timer, this timer is clocked on every second overflow/underflow of the
core timer T6. This configuration forms a 33-bit timer (16-bit core timer+T6OTL+16-bit
auxiliary timer).
The count directions of the two concatenated timers are not required to be the same. This
offers a wide variety of different configurations. T6 can operate in timer, gated timer or
counter mode in this case (see Figure 95).
GPT2 capture / reload register CAPREL in capture mode
This 16-bit register can be used as a capture register for the auxiliary timer T5. This mode is
selected by setting bit T5SC = ‘1’ in control register T5CON. Bit CT3 selects the external
input pin CAPIN or the input pins of timer T3 as the source for a capture trigger. Either a
positive, a negative, or both a positive and a negative transition at this pin can be selected to
trigger the capture function or transitions on input T3IN or input T3EUD or both inputs T3IN
and T3EUD. The active edge is controlled by bit-field CI in register T5CON. The maximum
input frequency for the capture trigger signal at CAPIN is f
CPU
/ 4. To ensure that a transition
of the capture trigger signal is correctly recognized, its level should be held for at least four
CPU clock cycles before it changes.
When the timer T3 capture trigger is enabled (CT3 = ‘1’) the CAPREL register captures the
contents of T5 upon transitions of the selected input(s). These values can be used to
measure T3’s input signals. This is useful when T3 operates in incremental interface mode,
in order to derive dynamic information (speed, acceleration, deceleration) from the input
signals.
When a selected transition at the external input pin (CAPIN, T3IN, T3EUD) is detected, the
contents of the auxiliary timer T5 is latched into register CAPREL, and interrupt request flag
CRIR is set. With the same event, timer T5 can be cleared to 0000h. This option is
controlled by bit T5CLR in register T5CON. If T5CLR = ‘0’, the contents of timer T5 are not
affected by a capture. If T5CLR = ‘1’, timer T5 is cleared after the current timer value has
been latched into register CAPREL.
Note: Bit T5SC only controls whether a capture is performed or not. If T5SC = ‘0’, the input pin
CAPIN can still be used to clear timer T5 or as an external interrupt input. This interrupt is
controlled by the CAPREL interrupt control register CRIC (see Figure 96).
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