CAN modules UM0404
454/564 DocID13284 Rev 2
Propagation time segment
This part of the bit time is used to compensate physical delay times within the network.
These delay times consist of the signal propagation time on the bus and the internal delay
time of the CAN nodes.
Any CAN node synchronized to the bit stream on the CAN bus will be out of phase with the
transmitter of that bit stream, caused by the signal propagation time between the two nodes.
The CAN protocol’s non-destructive bit wise arbitration and the dominant acknowledge bit
provided by receivers of CAN messages require that a CAN node transmitting a bit stream
must also be able to receive dominant bits transmitted by other CAN nodes that are
synchronized to that bit stream. The example in Figure 183 shows the phase shift and
propagation times between two CAN nodes.
Figure 183. The propagation time segment
In this example, both nodes A and B are transmitters performing an arbitration for the CAN
bus. The node A has sent its Start of Frame bit less than one bit time earlier than node B,
therefore node B has synchronized itself to the received edge from recessive to dominant.
Since node B has received this edge delay(A_to_B) after it has been transmitted, B’s bit
timing segments are shifted with regard to A. Node B sends an identifier with higher priority
and so it will win the arbitration at a specific identifier bit when it transmits a dominant bit
while node A transmits a recessive bit. The dominant bit transmitted by node B will arrive at
node A after the delay(B_to_A).
Due to oscillator (or PLL) tolerances, the actual position of node A’s Sample Point can be
anywhere inside the nominal range of node A’s Phase Buffer Segments, so the bit
transmitted by node B must arrive at node A before the start of Phase_Seg1. This condition
defines the length of Prop_Seg.
If the edge from recessive to dominant transmitted by node B would arrive at node A after
the start of Phase_Seg1, it could happen that node A samples a recessive bit instead of a
dominant bit, resulting in a bit error and the destruction of the current frame by an error flag.
The error occurs only when two nodes arbitrate for the CAN bus that have oscillators (or
PLL’s) of opposite ends of the tolerance range and that are separated by a long bus line; this
Sync_Seg
Prop_Seg Phase_Seg1 Phase_Seg2
Node B
Node A
Delay A_to_B Delay B_to_A
Prop_Seg ≥ Delay A_to_B + Delay B_to_A
Prop_Seg ≥ 2 • [max(node output delay + bus line delay + node input delay)]
Delay A_to_B ≥ node output delay(A) + bus line delay(A → B) + node input delay(B)
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