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UM0404 Memory organization
The ST10F276 also supports four different bus types:
• Multiplexed 16-bit Bus with address and data on PORT0 (Default after Reset)
• Multiplexed 8-bit Bus with address and data on PORT0 (P0L)
• De-multiplexed 16-bit Bus with address on PORT1 and data on PORT0
• De-multiplexed 8-bit Bus with address on PORT1 and data on PORT0 (P0L)
Memory model and bus mode are selected during reset by pin EA
and PORT0 pins. For
further details about the external bus configuration and control see Section 8: The external
bus interface on page 181.
External word and byte data can only be accessed via indirect or long 16-bit addressing
modes, using one of the four DPP registers. There is no short addressing mode for external
operands. Any word data access is made to an even byte address.
For PEC data transfers the external memory in segment 0 can be accessed independent of
the contents of the DPP registers via the PEC source and destination pointers.
The external memory is not provided for single bit storage therefore it is not bit addressable.
2.6 Crossing memory boundaries
The address space of the ST10F276 is implicitly divided into equally sized blocks of different
granularity and into logical memory areas. Crossing the boundaries between these blocks
(code or data) or areas requires special attention to ensure that the controller executes the
desired operations.
Memory Areas are partitions of the address space that represent different kinds of memory
(if provided at all). These memory areas are the IRAM/SFR area, the internal Flash Memory,
the on-chip X-Peripherals (if integrated) and the external memory.
Accessing subsequent data locations that belong to different memory areas is no problem.
However, when executing code, the different memory areas must be switched explicitly via
branch instructions. Sequential boundary crossing is not supported and leads to erroneous
results.
Note: Changing from the external memory area to the IRAM/SFR area takes place within
segment 0.
Segments are contiguous blocks of 64 Kbytes each. They are referenced via the code
segment pointer CSP for code fetches and via an explicit segment number for data
accesses overriding the standard DPP scheme.
During code fetching segments are not changed automatically, but rather must be switched
explicitly. The instructions JMPS, CALLS and RETS will do this.
In larger sequential programs make sure that the highest used code location of a segment
contains an unconditional branch instruction to the respective following segment, to prevent
the prefetcher from trying to leave the current segment.
Data Pages are contiguous blocks of 16 Kbytes each. They are referenced via the data
page pointers DPP3...0 and via an explicit data page number for data accesses overriding
the standard DPP scheme. Each DPP register can select one of the possible 1024 data
pages. The DPP register that is used for the current access is selected via the two upper
bits of the 16-bit data address. Subsequent 16-bit data addresses that cross the 16 Kbytes
data page boundaries therefore will use different data page pointers, while the physical
locations need not be subsequent within memory.
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